公开(公告)号：US09235258B2

公开(公告)日：2016-01-12

申请号：US14254413

申请日：2014-04-16

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32 ,  G06F12/08 ,  G06F11/14 ,  G11C7/10

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

公开(公告)号：US09223389B2

公开(公告)日：2015-12-29

申请号：US14496233

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32 ,  G06F12/08 ,  G06F11/14 ,  G11C7/10

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract translation: 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。