公开(公告)号：US20180157811A1

公开(公告)日：2018-06-07

申请号：US15884077

申请日：2018-01-30

申请人： Facebook, Inc.

发明人： Erick Tseng ,  Matthew Cahill

IPC分类号： G06F21/31 ,  H04M1/67 ,  G06F1/32 ,  H04M1/725

CPC分类号： G06F21/31 ,  G06F1/3206 ,  G06F1/3265 ,  H04M1/67 ,  H04M1/72552 ,  Y02B70/123 ,  Y02D10/153

摘要： In one embodiment, receiving a first action from a user of a computing device, wherein the first action causes the computing device to power up while a screen of the computing device is locked; obtaining a plurality of dynamic information items relevant to the user of the computing device; and displaying at least one of the plurality of dynamic information items on the locked screen of the computing device.

公开(公告)号：US20180157616A1

公开(公告)日：2018-06-07

申请号：US15887629

申请日：2018-02-02

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaegeun Yun ,  Lingling Liao ,  Bub-chul Jeong

IPC分类号： G06F13/42 ,  G06F13/364 ,  G06F1/10 ,  G06F1/32 ,  G06F13/28 ,  G06F13/40

CPC分类号： G06F13/4291 ,  G06F1/10 ,  G06F1/3237 ,  G06F13/28 ,  G06F13/364 ,  G06F13/405 ,  G06F13/4054 ,  G06F2213/0038 ,  Y02B70/12 ,  Y02B70/123 ,  Y02D10/128 ,  Y02D10/151

摘要： A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

公开(公告)号：US09971605B2

公开(公告)日：2018-05-15

申请号：US14281709

申请日：2014-05-19

申请人： VIA TECHNOLOGIES, INC.

发明人： G. Glenn Henry ,  Stephan Gaskins

IPC分类号： G06F9/44 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08 ,  H01L21/66

CPC分类号： G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

摘要： A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate multiple of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate a single processing core of the plurality of processing cores to be the bootstrap processor.

公开(公告)号：US09923451B2

公开(公告)日：2018-03-20

申请号：US15095885

申请日：2016-04-11

申请人： Futurewei Technologies, Inc.

发明人： Liming Ye ,  Heping Dai ,  Dianbo Fu

IPC分类号： H02M1/14 ,  H02M7/06 ,  G05F5/00

CPC分类号： H02M1/14 ,  G05F5/00 ,  H02M1/15 ,  H02M1/4266 ,  H02M7/066 ,  Y02B70/123

摘要： A configurable impedance circuit is provided, including a filter for filtering a received DC voltage and a controller. The filter includes a first capacitor, a second capacitor, and a selectable switch coupled in series with the second capacitor and coupled to receive a control signal. The selectable switch and the second capacitor are selectively coupled in parallel with the first capacitor. The controller is connected to sense a differential voltage across the second capacitor and configured to generate the control signal to open or close the selectable switch based on the differential voltage across the second capacitor, so as to maintain a voltage range across the second capacitor. According to disclosure of the present invention, the total physical size of the capacitors is reduced and the size of the power supply is reduced accordingly.

公开(公告)号：US09898303B2

公开(公告)日：2018-02-20

申请号：US14281585

申请日：2014-05-19

申请人： VIA TECHNOLOGIES, INC.

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06F12/08 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/44 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08 ,  H01L21/66

CPC分类号： G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

摘要： A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.

公开(公告)号：US09886567B2

公开(公告)日：2018-02-06

申请号：US13168598

申请日：2011-06-24

申请人： Erick Tseng ,  Matthew Cahill

发明人： Erick Tseng ,  Matthew Cahill

IPC分类号： G06F21/31 ,  G06F1/32 ,  H04M1/67 ,  H04M1/725

CPC分类号： G06F21/31 ,  G06F1/3206 ,  G06F1/3265 ,  H04M1/67 ,  H04M1/72552 ,  Y02B70/123 ,  Y02D10/153

摘要： In one embodiment, receiving a first action from a user of a computing device, wherein the first action causes the computing device to power up while a screen of the computing device is locked; obtaining a plurality of dynamic information items relevant to the user of the computing device; and displaying at least one of the plurality of dynamic information items on the locked screen of the computing device.

公开(公告)号：US09886080B2

公开(公告)日：2018-02-06

申请号：US14698255

申请日：2015-04-28

申请人： SanDisk Technologies Inc.

发明人： Anil Kumar Thadi Suryaprakash ,  Krishnamurthy Dhakshinamurthy ,  Ajay Dhingra ,  Rampraveen Somasundaram ,  Narendhiran Chinnaanangur Ravimohan ,  Bhavin Odedara ,  Srikanth Bojja ,  Jayanth Thimmaiah

IPC分类号： G06F3/00 ,  G06F13/12 ,  G06F13/42 ,  G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3253 ,  G06F1/3296 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/151 ,  Y02D10/172

摘要： A non-volatile memory system may include detection circuitry configured to detect that a host system is configured to initially communicate a clock signal and initialization command signals at a voltage level lower than its input/output driver circuit is configured to receive the signals. In response to the detection, the detection circuitry may switch a regulator circuit from a high voltage mode to a low voltage mode so that the input/output driver circuit is ready to receive the initialization commands at the lower voltage level.

公开(公告)号：US09886075B2

公开(公告)日：2018-02-06

申请号：US14967377

申请日：2015-12-14

申请人： Realtek Semiconductor Corp.

发明人： Hsuan-Ting Ho ,  Liang-Wei Huang ,  Heng Cheong Lao ,  Ta-Chin Tseng

IPC分类号： G06F1/32 ,  G06F13/42 ,  G06F1/26 ,  G06F13/40

CPC分类号： G06F1/3209 ,  G06F1/266 ,  G06F1/3253 ,  G06F13/40 ,  G06F13/42 ,  Y02B70/123 ,  Y02D10/151

摘要： A three-way handshaking method includes: controlling a first port in a first specific mode to send a first specific signal to a second port, and controlling the first port to enter a second specific mode; when the first port receives a second specific signal, determining the second port is in the second specific mode and controlling the first port to send a third specific signal to the second port; and when it is determined that the second port is in a third specific mode, controlling the first port to enter the third specific mode.

公开(公告)号：US09880602B2

公开(公告)日：2018-01-30

申请号：US14720503

申请日：2015-05-22

申请人： Seagate Technology LLC

发明人： Guy David Frick

IPC分类号： G06F1/28 ,  G06F1/32 ,  G06F3/06 ,  G06F11/20

CPC分类号： G06F1/28 ,  G06F1/3203 ,  G06F1/3221 ,  G06F1/3287 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0635 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0685 ,  G06F3/0689 ,  G06F11/2015 ,  G06F11/2094 ,  G06F2201/805 ,  Y02B70/123 ,  Y02D10/154

摘要： A mass data storage system includes a plurality of communicatively coupled storage drives powered by one or more power supplies. A power map defines the relationships between the storage drives and the power supplies and power rules/policies define the maximum permissible power load on each power supply at any point in time.

公开(公告)号：US09880583B2

公开(公告)日：2018-01-30

申请号：US14918397

申请日：2015-10-20

申请人： Ambiq Micro, Inc

发明人： Stephen James Sheafor ,  Scott Hanson ,  Donovan Popps

IPC分类号： G06F1/06 ,  G06F1/12 ,  G06F11/30 ,  G06F11/34 ,  G06F13/10 ,  G01R19/00 ,  G05F1/56 ,  H03K17/687 ,  H03M1/12 ,  H03L7/00 ,  G06F1/32

CPC分类号： G06F1/06 ,  G01R19/0084 ,  G05F1/56 ,  G05F1/575 ,  G06F1/12 ,  G06F1/3237 ,  G06F1/3287 ,  G06F1/3296 ,  G06F11/3041 ,  G06F11/3414 ,  G06F13/102 ,  H02M3/158 ,  H02M2001/0045 ,  H03K17/687 ,  H03L7/00 ,  H03L7/06 ,  H03L7/18 ,  H03L7/181 ,  H03M1/12 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/171

摘要： A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.