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公开(公告)号：US20230419093A1
公开(公告)日：2023-12-28
申请号：US17848136
申请日：2022-06-23
发明人： Pritish Narayanan , Geoffrey Burr
CPC分类号： G06N3/0635 , G06N3/0481 , G06F7/582 , H03M1/66
摘要： Techniques for generating digital outputs as stochastic bitstreams with activation function mapping are provided. In one aspect, a system includes: a shared circuitry component including a RNG for generating a sequence of random addresses to read a random sequence of digital voltage references stored in a LUT, and a DAC for converting the random sequence of digital voltage references into random analog voltage references VL; and a comparator(s) for comparing the random analog voltage references VL and input analog voltages VN in sequences of comparisons to produce sequences of digital pulses as stochastic bitstreams. A system having multiple comparators for simultaneously comparing each of the random analog voltage references VL against more than one of the input analog voltages VN in parallel is also provided, as is a method for generating digital outputs from input analog voltages VN.
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公开(公告)号：US20230306252A1
公开(公告)日：2023-09-28
申请号：US17704515
申请日：2022-03-25
摘要： A system comprises a processor, and a resistive processing unit (RPU) array. The RPU array comprises an array of cells which respectively comprise resistive memory devices that are programable to store weight values. The processor is configured to obtain a matrix comprising target weight values, program cells of the array of cells to store weight values in the RPU array, which correspond to respective target weight values of the matrix, and perform a calibration process to calibrate the RPU array. The calibration process comprises iteratively adjusting the target weight values of the matrix, and reprogramming the stored weight values of the matrix in the RPU array based on the respective adjusted target weight values, to reduce a variation between output lines of the RPU array with respect to multiply-and-accumulate distribution data that is generated and output from respective output lines of the RPU array during the calibration process.
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公开(公告)号：US20230178150A1
公开(公告)日：2023-06-08
申请号：US17545671
申请日：2021-12-08
CPC分类号： G11C13/0061 , G11C13/0004 , G06F13/4022 , G06F13/1684
摘要： A computer-implemented method, according to one embodiment, includes: causing a first subset of pulse width modulators in a crossbar array of memory cells to apply respective pulses to the crossbar array together at a same start time and end the respective pulses according to a predetermined distribution of times correlated to stored pulse width data for each pulse width modulator. The method also includes causing a second subset of pulse width modulators in the crossbar array to apply pulses to the crossbar array according to the predetermined distribution of times correlated to stored pulse width data for each pulse width modulator and end the respective pulses together at a same end time.
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公开(公告)号：US20230100139A1
公开(公告)日：2023-03-30
申请号：US18061074
申请日：2022-12-02
发明人： HsinYu Tsai , Geoffrey Burr , Pritish Narayanan
IPC分类号： G06N3/08
摘要： Implementing a convolutional neural network (CNN) includes configuring a crosspoint array to implement a convolution layer in the CNN. Convolution kernels of the layer are stored in crosspoint devices of the array. Computations for the CNN are performed by iterating a set of operations for a predetermined number of times. The operations include transmitting voltage pulses corresponding to a subpart of a vector of input data to the crosspoint array. The voltage pulses generate electric currents that are representative of performing multiplication operations at the crosspoint device based on weight values stored at the crosspoint devices. A set of integrators accumulates an electric charge based on the output electric currents from the respective crosspoint devices. The crosspoint array outputs the accumulated charge after iterating for the predetermined number of times. The accumulated charge represents a multiply-add result of the vector of input data and the one or more convolution kernels.
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公开(公告)号：US11461640B2
公开(公告)日：2022-10-04
申请号：US16388320
申请日：2019-04-18
摘要： Methods and systems for performing calculations with a neural network include determining a conductance drift coefficient for resistive processing unit (RPU) weights in a neural network. A correction factor is applied to neuron inputs in the neural network in accordance with the drift coefficient and a time that has elapsed since the RPU weights were programmed. A calculation is performed with the neural network. The correction factor compensates for conductance drift.
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公开(公告)号：US11183238B2
公开(公告)日：2021-11-23
申请号：US16554018
申请日：2019-08-28
发明人： Geoffrey Burr
摘要： A computer-implemented method for suppressing outlier drift of a phase change memory (PCM) device includes programming, by a controller, a conductance of the PCM device, wherein the programming includes configuring the conductance of the PCM device to a first conductance value at a first time-point, the first time-point being a programming time-point. The programming further includes determining, at a first pre-compensation time-point, that the conductance of the PCM device has changed to a second conductance value that differs from a target conductance value by no more than a predetermined threshold. Further, the programming includes, based on the above determination, reprogramming the PCM device to the first conductance value at a second time-point, including measuring said pre-compensation again, but at a second pre-compensation time-point.
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公开(公告)号：US10460237B2
公开(公告)日：2019-10-29
申请号：US14954468
申请日：2015-11-30
摘要： Artificial neural networks (ANNs) are a distributed computing model in which computation is accomplished using many simple processing units (called neurons) and the data embodied by the connections between neurons (called synapses) and the strength of these connections (called synaptic weights). An attractive implementation of ANNs uses the conductance of non-volatile memory (NVM) elements to code the synaptic weight. In this application, the non-idealities in the response of the NVM (such as nonlinearity, saturation, stochasticity and asymmetry in response to programming pulses) lead to reduced network performance compared to an ideal network implementation. Disclosed is a method that improves performance by implementing a learning rate parameter that is local to each synaptic connection, a method for tuning this local learning rate, and an implementation that does not compromise the ability to train many synaptic weights in parallel during learning.
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28.发明公开公开(公告)号：US20240361797A1
公开(公告)日：2024-10-31
申请号：US18140107
申请日：2023-04-27
CPC分类号： G06F1/03 , G06F7/5443 , G06N3/048
摘要： Special-purpose digital-compute hardware for fully-programmable look-up-tables is provided. In one aspect, a system for implementing a continuous function by piecewise linear approximation includes: at least one memory programmatically loaded with an indexed table of slope/intercept values of linear segments along a gradient of the continuous function approximating a plurality of contiguous ranges of the continuous function; at least one Bin ID logic having data registers programmatically loaded with bin-threshold values corresponding to the plurality of contiguous ranges defining a series of arbitrarily-spaced bins; and a Fused-Multiply-Add circuit configured to multiply an incoming data element by a slope value and add an intercept value from the indexed table of slope/intercept values selected based on the bin-threshold values. Comparators in the Bin ID logic can be configured to compare the incoming data-element with the bin-threshold values. A method for implementing a continuous function by piecewise linear approximation is also provided.
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公开(公告)号：US20240202275A1
公开(公告)日：2024-06-20
申请号：US18085011
申请日：2022-12-20
CPC分类号： G06F12/0207 , G06F17/16
摘要： A system, method and computer program product for assigning deep neural network (DNN) weight matrices to a Compute-in-Memory (CiM) accelerator system, and particularly, efficient allocation strategies for assigning DNN model weight-layers to two-dimensional (2D) tiers of three-dimensional (3D) crossbar array tiles. Such efficient allocation strategies for assigning DNN model weight-layers to tiers and tiles of a CiM accelerator are optimized to minimize contention, latency and dead-time, and to maximize accelerator throughput. In one scenario, efficient allocation strategies include assigning DNN weight matrices to the 2D tiers of a 3D crossbar array tile to maximize throughput and minimize completion latency for a finite-batch-size example of an incoming workflow. In a further scenario, efficient allocation strategies assign DNN weight matrices to the 2D tiers of a 3D crossbar array tile to minimize dead-time-latency-before-next-batch-member-can-be-input in an infinite-batch-size or a continuous workflow scenario.
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30.发明公开公开(公告)号：US20240086677A1
公开(公告)日：2024-03-14
申请号：US17931538
申请日：2022-09-12
摘要： A method includes receiving, at a neural network weight layer of an artificial neural network, an incoming excitation vector. The artificial neural network includes one or more operations requiring one or more scalar values, such as a mean or a standard deviation, to be computed across an output data vector of the artificial neural network. The method further includes using a predicted representation of the one or more scalar values during forward inference of the artificial neural network by the incoming excitation vector to apply the one or more operations to the output data vector, thus avoiding any computation needed to compute an exact representation of the one or more scalar values from the output data vector.
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