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21.发明授权Method and apparatus for electronically aligning capacitively coupled chip pads 有权用于电子对准电容耦合芯片焊盘的方法和装置公开(公告)号：US06812046B2
公开(公告)日：2004-11-02
申请号：US10207671
申请日：2002-07-29
IPC分类号： H01L2166
CPC分类号： H04B5/0012 , G06F17/5077 , H01L23/48 , H01L23/544 , H01L2223/54473 , H01L2225/06531 , H01L2924/0002 , H01L2924/0001
摘要： One embodiment of the present invention provides a system that electronically aligns pads on different semiconductor chips to facilitate communication between the semiconductor chips through capacitive coupling. The system operates by measuring an alignment between a first chip and a second chip, wherein the first chip is situated face-to-face with the second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip. Next, the system uses the measured alignment to associate transmitter pads on the first chip with proximate receiver pads on the second chip. The system then selectively routes data signals to transmitter pads on the first chip so that the data signals are communicated through capacitive coupling to intended receiver pads in the second chip that are proximate to the transmitter pads.
摘要翻译： 本发明的一个实施例提供一种系统，其电子地对准不同半导体芯片上的焊盘，以便于通过电容耦合在半导体芯片之间进行通信。 该系统通过测量第一芯片和第二芯片之间的对准来工作，其中第一芯片与第二芯片面对面设置，使得第一芯片上的发射器焊盘与第二芯片上的接收器焊盘电容耦合。 接下来，系统使用测量的对准来将第一芯片上的发射器焊盘与第二芯片上的接近焊盘相关联。 然后，系统选择性地将数据信号路由到第一芯片上的发射机焊盘，使得数据信号通过电容耦合传递到靠近发射器焊盘的第二芯片中的预期接收器焊盘。
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22.发明授权公开(公告)号：US06707317B2
公开(公告)日：2004-03-16
申请号：US10135166
申请日：2002-04-29
IPC分类号： H03K19096
CPC分类号： H03K19/0966
摘要： One embodiment of the present invention provides a domino logic circuit that operates asynchronously. This domino logic circuit includes a number of stages, including a present stage that receives one or more inputs from a prior stage and generates one or more outputs for a next stage. It also includes a control circuit that ensures that the present stage enters a precharging state before entering a subsequent evaluation state in which one or more inputs of the present stage are used to generate one or more outputs. This control circuit receives a prior control signal from the prior stage and sends a present control signal to the next stage
摘要翻译： 本发明的一个实施例提供了一种异步操作的多米诺逻辑电路。 该多米诺骨牌逻辑电路包括多个级，包括从现有级接收一个或多个输入并为下一级生成一个或多个输出的当前级。 它还包括控制电路，其确保当前级在进入后级评估状态之前进入预充电状态，其中使用当前级的一个或多个输入来产生一个或多个输出。 该控制电路接收来自前一级的先前控制信号，并将当前控制信号发送到下一级
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公开(公告)号：US6072805A
公开(公告)日：2000-06-06
申请号：US884927
申请日：1997-06-30
IPC分类号： H04J3/02
CPC分类号： G06F13/364
摘要： An arbiter is disclosed for determining a sequence of signals indicative of events occurring variously on at least two input connections. The arbiter includes a first input connection and a second input connection for carrying the signals indicative of events. A first input queue for storing representations of events that are waiting to be processed is connected to the first input connection, and a second input queue also for storing representations of events that are waiting to be processed is connected to the second input connection. An arbitration circuit coupled to the first input queue and to the second input queue receives the representations of events from each of the queues and determines the temporal order of occurrence of the event representations in the queues when the events arrive at time intervals greater than a specified amount, and arbitrarily assigns a sequence to one or the other of the events from the queues when the events arrive at time intervals equal to or less than the specified amount. In response the arbitration circuit reports the temporal order or arbitrary sequence as a sequence of output signals and removes each event representation from the appropriate queue when reporting its temporal order or sequence.
摘要翻译： 公开了一种用于确定指示在至少两个输入连接上不同地发生的事件的信号序列的仲裁器。 仲裁器包括用于承载指示事件的信号的第一输入连接和第二输入连接。 用于存储等待被处理的事件的表示的第一输入队列连接到第一输入连接，并且还用于存储等待被处理的事件的表示的第二输入队列连接到第二输入连接。 耦合到第一输入队列和第二输入队列的仲裁电路从每个队列接收事件的表示，并且当事件以大于指定的时间间隔的时间间隔到达时，确定队列中的事件表示的出现的时间顺序 量，并且当事件以等于或小于指定量的时间间隔到达时，将序列任意地分配给队列中的一个或另一个事件。 作为响应，仲裁电路将时间顺序或任意序列报告为输出信号的序列，并在报告其时间顺序或序列时从适当的队列中移除每个事件表示。
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公开(公告)号：US5861762A
公开(公告)日：1999-01-19
申请号：US813054
申请日：1997-03-07
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： H03K19/21 , H03K19/0948
CPC分类号： H03K19/215
摘要： A four transistor XOR or XNOR gate includes an inverting stage and a non-inverting stage. The transistors in each stage are coupled so as to enable changing inputs and existing inputs to drive the output in the same direction. The XOR gate and XNOR gate take advantage of a known order or inputs to reduce the delay of the gate.
摘要翻译： 四极晶体管XOR或XNOR门包括反相级和非反相级。 每个级中的晶体管被耦合，以便能够改变输入和现有输入以在相同方向上驱动输出。 XOR门和XNOR门利用已知的顺序或输入来减少门的延迟。
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公开(公告)号：US4679213A
公开(公告)日：1987-07-07
申请号：US689635
申请日：1985-01-08
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
CPC分类号： G11C19/00
摘要： A queue form of asynchronous register is disclosed with signal paths commonly carrying elements of both data and control. Binaries are intercoupled in two sequences and are individually cross coupled to register "one" bits in one sequence and "zero" bits in the other. Bits are manifest by signal level changes. Individual binaries are driven by logic to accomplish an operational rule based on the states of neighboring binaries in both sequences. Each binary in each sequence is controlled by the states of the predecessor and successor in its sequence and the predecessor and successor of its associated binary in the other sequence. Specifically, if predecessor and successor binaries in a sequence are in different states, and predecessor and successor binaries of an associated binary in the other sequence are in the same state, the state of the predecessor is to be taken.
摘要翻译： 披露了具有通常携带数据和控制元素的信号路径的异步寄存器的队列形式。 二进制序列以两个序列相互配合，并且被单独交叉耦合以在一个序列中寄存“一个”比特，而在另一个序列中“零”比特。 位由信号电平变化表现。 单个二进制文件由逻辑驱动，以基于两个序列中的相邻二进制文件的状态来完成操作规则。 每个序列中的每个二进制由其序列中的前导和后继的状态以及在其他序列中的相关二进制的前导和后继来控制。 具体来说，如果序列中的前导和后继二进制文件处于不同的状态，并且其他序列中相关联的二进制文件的前导和后继二进制文件处于相同的状态，则将采用前导的状态。
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公开(公告)号：US4209240A
公开(公告)日：1980-06-24
申请号：US949756
申请日：1978-10-10
CPC分类号： G03F7/704
摘要： An apparatus and method are described for applying a light beam in an extremely precise pattern to a work piece, such as a photographic plate or reticle on which an integrated circuit pattern is to be formed and which will be then utilized to produce integrated circuits. The method includes moving a very narrow beam light source relative to the reticle in a scanning pattern such as an X-Y raster pattern, accurately sensing the relative positions of the light source to the reticle as by the use of laser interferometers, and briefly energizing the light source only when it lies at the locations to be exposed. The light source is energized while it moves, so it is not necessary to stop the light source at precisely located positions. The light source can be moved relative to the reticle, by mounting the light source on a flexible plate that oscillates in substantially a straight line, and by mounting the reticle on another flexible plate that moves perpendicular to the light source and that can be very slowly advanced perpendicular to the oscillating light source, so that after a period of time the light source has moved over every point of the reticle, although only a minority of the points normally will have been exposed.
摘要翻译： 描述了一种用于以非常精确的图案将光束施加到工件（例如要在其上形成集成电路图案的照相板或标线片）上并随后用于产生集成电路的装置和方法。 该方法包括以诸如XY光栅图案的扫描图案相对于掩模版移动非常窄的光束光源，通过使用激光干涉仪精确地感测光源到掩模版的相对位置，并且短暂地激励光 只有当它位于要暴露的位置时才能使用。 光源在移动时被通电，因此不需要在精确定位的位置停止光源。 光源可以通过将光源安装在基本上直线上振荡的柔性板上，并且通过将光罩安装在垂直于光源移动的另一柔性板上并且可以非常缓慢地相对于光罩移动 垂直于振荡光源前进，使得在一段时间之后光源已经移动到标线的每个点上，尽管只有少数点通常将被曝光。
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公开(公告)号：US20130080815A1
公开(公告)日：2013-03-28
申请号：US13239957
申请日：2011-09-22
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： G06F1/12
摘要： An integrated circuit includes a first pipeline with multiple stages of asynchronous circuits. Note that a stage in the first pipeline communicates with a stage in a corresponding second pipeline with multiple stages of asynchronous circuits on another integrated circuit via connectors. Furthermore, a first state wire preceding the stage in the first pipeline provides advanced notice to a first state wire preceding the stage in the second pipeline of subsequent communication between the stage in the first pipeline and the stage in the second pipeline so that the stage in the second pipeline has time to amplify a signal received from the stage in the first pipeline, thereby facilitating approximately synchronous operation of the stages in the first and second pipelines.
摘要翻译： 集成电路包括具有多级异步电路的第一流水线。 注意，第一流水线中的一级通过连接器与另一集成电路上的多级异步电路的相应的第二管线中的级通信。 此外，第一管线中的级之前的第一状态线将第一管线中的级与第二管线中的级之间的后续通信的第二管道中的级之间的第一状态引线提前通知， 第二管线有时间放大从第一管道中的级接收的信号，从而便于第一和第二管道中的级的大致同步操作。
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公开(公告)号：US07012459B2
公开(公告)日：2006-03-14
申请号：US10442392
申请日：2003-05-20
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
CPC分类号： G05D23/1951
摘要： One embodiment of the present invention provides a system that regulates heat within an asynchronous circuit. During operation, the system monitors a temperature within the asynchronous circuit. If the temperature exceeds a threshold value, the system introduces a delay into the asynchronous circuit that causes signals to propagate more slowly through the asynchronous circuit. This causes circuit elements within the asynchronous circuit to switch less frequently and consequently causes the circuit elements to generate less heat.
摘要翻译： 本发明的一个实施例提供一种调节异步电路内的热量的系统。 在运行期间，系统监视异步电路内的温度。 如果温度超过阈值，系统将引入延迟到异步电路，使得信号通过异步电路传播得更慢。 这导致异步电路内的电路元件更不频繁地切换，并且因此导致电路元件产生较少的热量。
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公开(公告)号：US06847247B2
公开(公告)日：2005-01-25
申请号：US10304667
申请日：2002-11-25
申请人： Ian W. Jones , Ivan E. Sutherland
发明人： Ian W. Jones , Ivan E. Sutherland
摘要： A plurality of clock signal phases are distributed to a circuit and at least one jitter source is coupled between at least two selected clock phases of the plurality of clock signal phases to introduce a jitter between at least the selected two clock signal phases. In a specific embodiment, the clock distribution system provides N clock phases and, if the phases have an order, there is one jitter source provided between each of the first N−1 phases and the following phase, so that each phase has a jitter relative to each other phase. Several implementations are possible for the jitter sources, which can be noise sources or pseudo-random noise sources, depending on which is easier to design and implement in a specific clock distribution system.
摘要翻译： 多个时钟信号相位被分配到电路，并且至少一个抖动源耦合在多个时钟信号相位的至少两个选定的时钟相位之间，以在至少所选择的两个时钟信号相位之间引入抖动。 在具体实施例中，时钟分配系统提供N个时钟相位，并且如果相位有顺序，则在第一N-1个相位和随后的相位之间提供一个抖动源，使得每个相位具有抖动相对 到彼此相位。 抖动源的几种实现方式是可能的，抖动源可以是噪声源或伪随机噪声源，这取决于在特定的时钟分配系统中更易于设计和实现的抖动源。
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公开(公告)号：US06769007B2
公开(公告)日：2004-07-27
申请号：US09827569
申请日：2001-04-05
IPC分类号： G06F750
CPC分类号： G06F7/508
摘要： One embodiment of the present invention provides an apparatus for facilitating an addition operation between two N-bit numbers, wherein the apparatus has a regular structure. The apparatus includes a carry circuit for generating at least one carry signal for the addition operation, wherein the carry circuit includes a plurality of logic blocks organized into rows that form approximately logN successive stages of logic blocks. Each of these logic blocks provides current for at most a constant number of inputs in a successive stage of logic blocks. Additionally, within a given stage of logic blocks, outputs from multiple logic blocks are ganged together to drive a signal line that feeds multiple inputs in a successive stage of logic blocks. Furthermore, there are at most a constant number of lateral tracks in a planar layout of signal lines between the successive stages of logic blocks. Hence, the present invention can reduce layout and design effort, while producing a regularized layout that takes up a small amount of space on a semiconductor chip.
摘要翻译： 本发明的一个实施例提供了一种用于促进两个N位数之间的相加操作的装置，其中该装置具有规则的结构。 该装置包括用于产生用于加法运算的至少一个进位信号的进位电路，其中进位电路包括多个组合成行的逻辑块，其形成大约logN的逻辑块的连续级。 这些逻辑块中的每一个在逻辑块的连续级中提供最多恒定数量的输入的电流。 此外，在逻辑块的给定阶段内，来自多个逻辑块的输出被组合在一起以驱动在逻辑块的连续级中馈送多个输入的信号线。 此外，在逻辑块的连续级之间的信号线的平面布局中，存在至多一定数量的横向轨道。 因此，本发明可以减少布局和设计工作，同时产生在半导体芯片上占用少量空间的正规化布局。
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