公开(公告)号：US07636361B1

公开(公告)日：2009-12-22

申请号：US11242113

申请日：2005-09-27

申请人： Jo C. Ebergen ,  Justin M. Schauer ,  Robert D. Hopkins ,  Ivan E. Sutherland

发明人： Jo C. Ebergen ,  Justin M. Schauer ,  Robert D. Hopkins ,  Ivan E. Sutherland

IPC分类号： H04L12/28

CPC分类号： H04L49/40

摘要： One embodiment of the present invention provides a system that asynchronously controls sending data items from a sender to a receiver. This system includes a set of sending FIFOs, a set of receiving FIFOs, as well as a shared data path between the sender and the receiver. The system also includes a set of control paths that operate in parallel between the sender and the receiver, wherein a given control path controls the transmission of data items between a corresponding sending FIFO and a corresponding receiving FIFO through the shared data path. The system further includes a round-robin scheduling mechanism which activates one control path at a time in a predetermined sequence. An activated control path asynchronously controls the sending of a data item from a corresponding sending FIFO to a corresponding receiving FIFO. By operating the control paths in parallel in the predetermined sequence, the system does not have to wait a request-acknowledge cycle time between the sender and the receiver before sending consecutive data items through the shared data path, but can instead send multiple data items through the shared data path within a single request-acknowledge cycle time.

摘要翻译： 本发明的一个实施例提供了一种异步地控制从发送器到接收器发送数据项的系统。 该系统包括一组发送FIFO，一组接收FIFO，以及发送器和接收器之间的共享数据路径。 该系统还包括在发送器和接收器之间并行操作的一组控制路径，其中给定的控制路径通过共享数据路径来控制在对应的发送FIFO和对应的接收FIFO之间的数据项的传输。 该系统还包括循环调度机制，其以预定的顺序一次激活一个控制路径。 激活的控制路径异步地控制将数据项从相应的发送FIFO发送到相应的接收FIFO。 通过以预定的顺序并行地操作控制路径，系统在发送连续数据项之前不必等待发送方和接收方之间的请求确认周期时间，而是可以通过共享数据路径发送多个数据项 在单个请求确认周期时间内的共享数据路径。

公开(公告)号：US07384804B2

公开(公告)日：2008-06-10

申请号：US11125792

申请日：2005-05-09

申请人： Robert J. Drost ,  Ivan E. Sutherland ,  William S. Coates

发明人： Robert J. Drost ,  Ivan E. Sutherland ,  William S. Coates

IPC分类号： H01L21/66

CPC分类号： H01L25/0657 ,  H01L23/48 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01067 ,  H01L2224/0401

摘要： One embodiment of the present invention provides a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system measures an alignment between a first chip and a second chip. The system then selects a group of transmitter mini-bars on the first chip to form a transmitter bit position based on the measured alignment. In this way, the system allows a data signal to be distributed to and transmitted by the mini-bars that form the transmitter bit position. The system also selects a group of receiver mini-bars on the second chip to form a receiver bit position based on the measured alignment. Next, the system associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip based on the measured alignment. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.

摘要翻译： 本发明的一个实施例提供了一种系统，其电子地对准位于面对面的不同半导体芯片上的迷你条，以促进半导体芯片之间通过电容耦合的通信。 在操作期间，系统测量第一芯片和第二芯片之间的对准。 然后，系统在第一芯片上选择一组发射器迷你条，以基于测量的对准来形成发射机位置。 以这种方式，该系统允许将数据信号分配到形成发送器位位置的迷你条并发送。 该系统还在第二芯片上选择一组接收器迷你条，以形成基于测量对准的接收器位位置。 接下来，系统基于测量的对准将第一芯片上的发射机位位置与第二芯片上的接收器位置相关联。 以这种方式，系统允许由第一芯片上的发送器位置内的迷你条发送的数据信号由第二芯片上相关联的接收器位位置内的迷你条集中接收。

公开(公告)号：US07026867B2

公开(公告)日：2006-04-11

申请号：US10879606

申请日：2004-06-28

申请人： Robert J. Drost ,  Ronald Ho ,  Ivan E. Sutherland

发明人： Robert J. Drost ,  Ronald Ho ,  Ivan E. Sutherland

IPC分类号： H03F1/02

CPC分类号： H03F3/45977 ,  H03F3/08

摘要： One embodiment of the present invention provides a capacitively-coupled receiver amplifier that has an input with no DC coupling. A DC voltage is programmed on the input. During programming, a transmitter is held at a voltage at a midpoint between a voltage that represents a logical “1” and a voltage that represents a logical “0” and the input voltage of the receiver amplifier is programmed to be substantially the switching-threshold voltage for the receiver amplifier. Then, during normal data communication, the transmitter drives high and low electrical signals that are coupled to the receiver amplifier. Since the input of the receiver amplifier has been substantially set to the DC voltage, the receiver amplifier need not control the DC voltage of the input for each transition in the electrical signals.

摘要翻译： 本发明的一个实施例提供一种具有不具有直流耦合的输入的电容耦合接收放大器。 在输入端编程一个直流电压。 在编程期间，发射机被保持在表示逻辑“1”的电压和表示逻辑“0”的电压之间的中点处的电压，并且接收机放大器的输入电压被编程为基本上是切换阈值 接收放大器的电压。 然后，在正常数据通信期间，发射机驱动耦合到接收放大器的高电平和低电信号。 由于接收机放大器的输入已基本设置为直流电压，所以接收放大器不需要控制电信号中每个转换的输入的直流电压。

公开(公告)号：US07020779B1

公开(公告)日：2006-03-28

申请号：US09644086

申请日：2000-08-22

申请人： Ivan E. Sutherland

发明人： Ivan E. Sutherland

IPC分类号： H04K1/00 ,  H04L9/00

CPC分类号： H04L63/0428 ,  H04L63/062

摘要： An e-mail handling system, wherein e-mail messages are entered, transported and stored, comprises a central key repository, means for encrypting a message using a key associated with the message, means for adding the key to the central key repository; and means for deleting the key for a message when the message is to be made unrecallable.

摘要翻译： 一种电子邮件处理系统，其中输入，传输和存储电子邮件消息，包括中央密钥存储库，用于使用与该消息相关联的密钥加密消息的装置，用于将密钥添加到中央密钥存储库的装置; 以及当消息被做成不可呼叫时，删除消息的密钥的装置。

公开(公告)号：US06987412B2

公开(公告)日：2006-01-17

申请号：US10816761

申请日：2004-04-02

申请人： Ivan E. Sutherland ,  Robert J. Bosnyak ,  Robert J. Drost

发明人： Ivan E. Sutherland ,  Robert J. Bosnyak ,  Robert J. Drost

IPC分类号： H03K3/356 ,  H03L5/00

CPC分类号： H03K5/003 ,  H01L23/48 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2924/00013 ,  H01L2924/0002 ,  H03K3/037 ,  H03K17/689 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A system is presented for latching and amplifying a capacitively coupled inter-chip communication signal that operates by receiving an input signal on a capacitive receiver pad and feeding the input signal through an inverter to produce an output signal. The output signal is fed back through a weakened inverter to produce a feedback signal that is fed into an input of the inverter to form a latch for the input signal. The weakened inverter is biased to produce a feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL. VH is set slightly higher than the switching threshold of the inverter, and VL is set slightly lower than the switching threshold. This feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal.

摘要翻译： 提出了一种用于锁存和放大电容耦合的芯片间通信信号的系统，其通过接收电容性接收器焊盘上的输入信号并通过反相器馈送输入信号以产生输出信号来操作。 输出信号通过弱化逆变器反馈，产生反馈信号，该反馈信号馈送到反相器的输入端，形成输入信号的锁存器。 弱化的逆变器被偏置以产生在高偏置电压V H H和低偏压V L之间摆动的反馈信号。 V H设定得比逆变器的切换阈值略高，并且将V L L设定得比切换阈值略低。 该反馈信号使得输入信号驻留在接近逆变器的开关阈值的窄电压范围内，从而使得反相器对输入信号中的小转变敏感。

公开(公告)号：US06825708B1

公开(公告)日：2004-11-30

申请号：US10697914

申请日：2003-10-29

申请人： Robert J. Drost ,  Ivan E. Sutherland

发明人： Robert J. Drost ,  Ivan E. Sutherland

IPC分类号： G06G712

CPC分类号： H03K5/003 ,  H01L23/48 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03F1/301 ,  H03F1/342 ,  H01L2924/00

摘要： An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.

摘要翻译： 一种用于消除偏移电压的感测电路的装置和方法。 具体地，在一个实施例中，CMOS反相放大器放大存在于输入节点处的输入信号。 电阻反馈电路耦合到CMOS反相放大器，用于消除与CMOS反相放大器相关联的偏移电压。 这通过将CMOS反相放大器偏置到其阈值电压来实现。 偏置电路耦合到电阻反馈电路，用于在亚阈值导通区域偏置电阻反馈电路中的MOSFET晶体管。 因此，电阻反馈电路对输入节点呈现高阻抗。 耦合到电阻反馈电路的钳位电路在亚阈值导通区域中保持电阻反馈电路中的晶体管的操作。

公开(公告)号：US06559531B1

公开(公告)日：2003-05-06

申请号：US09418120

申请日：1999-10-14

申请人： Ivan E. Sutherland

发明人： Ivan E. Sutherland

IPC分类号： H01L2302

CPC分类号： H01L23/642 ,  H01L23/48 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/3025

摘要： An integrated circuit device includes first and second arrays of semiconductor dice. Each array of dice is arranged in face-to-face relation to the other array of dice, thus forming a lower layer of dice and an upper layer of dice. The layers are aligned so that each upper layer die straddles two or more of the lower layer dice, thus defining overlap regions. In the overlap regions, signal pads of one layer are aligned with corresponding signal pads of the other layer. The two layers are spaced apart, thus creating a capacitance-based communication path between the upper and lower layers via the signal paths.

摘要翻译： 集成电路器件包括半导体晶片的第一和第二阵列。 每个骰子阵列与另一个骰子阵列面对面地布置，从而形成下层骰子和上层骰子。 这些层被对准，使得每个上层模具跨越下层骰子中的两个或更多个，从而限定重叠区域。 在重叠区域中，一层的信号焊盘与另一层的相应信号焊盘对准。 两层间隔开，从而通过信号路径在上层和下层之间产生基于电容的连通路径。

公开(公告)号：US06486709B2

公开(公告)日：2002-11-26

申请号：US09854094

申请日：2001-05-11

申请人： Ivan E. Sutherland ,  Josephus C. Ebergen

发明人： Ivan E. Sutherland ,  Josephus C. Ebergen

IPC分类号： H03K1920

CPC分类号： G05B19/045 ,  G05B2219/23289 ,  G05B2219/25263 ,  G05B2219/25306

摘要： One embodiment of the present invention provides a system that asynchronously distributes data to a plurality of destinations within a digital circuit. Upon receiving a data item to be distributed, the system monitors asynchronous control signals associated with the destinations, wherein a given asynchronous control signal indicates that a given destination is free to receive the data item. For each destination that is free to receive the data item, the system forwards the data item to the destination asynchronously without waiting for a system clock signal, and also changes an asynchronous control signal associated with the destination to indicate that the destination is not free to receive a subsequent data item.

公开(公告)号：US06356117B1

公开(公告)日：2002-03-12

申请号：US09676428

申请日：2000-09-29

申请人： Ivan E. Sutherland ,  Scott M. Fairbanks ,  Josephus C. Ebergen

发明人： Ivan E. Sutherland ,  Scott M. Fairbanks ,  Josephus C. Ebergen

IPC分类号： H03K1900

CPC分类号： G06F7/00

摘要： One embodiment of the present invention provides a system for controlling asynchronous data transfers within a circuit. This system operates by monitoring a first voltage level on a first conductor that specifies whether a first stage of the circuit contains data. The system also monitors a second voltage level on a second conductor that specifies whether a second stage of the circuit contains data. Upon detecting that the first voltage level indicates that first stage contains data to be transmitted to the second stage, and that the second voltage level indicates that the second stage does not contain data, and is therefore available to receive data from the first stage, the system transfers the data from the first stage to the second stage. This is accomplished by generating a second stage latch signal to latch data into the second stage from the first stage. It also involves changing the first voltage level to indicate that the first stage no longer contains data, and changing the second voltage level to indicate that the second stage contains data.

摘要翻译： 本发明的一个实施例提供一种用于控制电路内的异步数据传输的系统。 该系统通过监视指定电路的第一级是否包含数据的第一导体上的第一电压电平来操作。 该系统还监视第二导体上的第二电压电平，其指定电路的第二级是否包含数据。 当检测到第一电压电平指示第一级包含要发送到第二级的数据，并且第二电压电平指示第二级不包含数据，并且因此可用于从第一级接收数据时， 系统将数据从第一阶段转移到第二阶段。 这是通过产生第二级锁存信号来实现的，以将数据从第一级锁存到第二级。 它还包括改变第一电压电平以指示第一级不再包含数据，并且改变第二电压电平以指示第二级包含数据。

公开(公告)号：US06351261B1

公开(公告)日：2002-02-26

申请号：US08114546

申请日：1993-08-31

申请人： Bruce A. Reichlen ,  Ivan E. Sutherland

发明人： Bruce A. Reichlen ,  Ivan E. Sutherland

IPC分类号： G06F1700

CPC分类号： G06F3/011

摘要： A computer video display system and method is disclosed. The computer video display system includes a frame buffer for storing a multiplicity of view points of a model to be displayed, a measurement device for measuring an aspect of the user's movement, a view point device for ascertaining a point of view of the model to be displayed in response to the measurement device, a computational device for modifying the view point according to a predefined algorithm, an access device for accessing the appropriate display information from the frame buffer, and a head mounted display for displaying the selected view point of the model. During operation, the measuring device, the view point device, and the computational device continuously update the view points of the model in response to movements of the user. In response thereto, the access device traverses the frame buffer and provides the updated display information to the head mounted display. The image, as seen through the head mounted display, appears to be continuous, fluid and natural.

摘要翻译： 公开了一种计算机视频显示系统和方法。 计算机视频显示系统包括用于存储要显示的模型的多个视点的帧缓冲器，用于测量用户移动方面的测量装置，用于确定模型的观点的视点装置 响应于测量装置而显示的计算装置，用于根据预定义的算法修改视点的计算装置，用于从帧缓冲器访问适当的显示信息的访问装置以及用于显示模型的所选视点的头戴式显示器 。 在操作期间，测量装置，视点装置和计算装置响应于用户的移动持续地更新模型的视点。 响应于此，访问设备遍历帧缓冲器并将更新的显示信息提供给头戴式显示器。 通过头戴式显示器看到的图像似乎是连续的，流畅的和自然的。