公开(公告)号：US20240186295A1

公开(公告)日：2024-06-06

申请号：US18439693

申请日：2024-02-12

Applicant: Lodestar Licensing Group LLC

Inventor： Randon K. Richards ,  Aparna U. Limaye ,  Owen R. Fay ,  Dong Soon Lim

IPC: H01L25/065 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L23/66 ,  H01L25/00 ,  H01L25/18 ,  H01Q1/22 ,  H01Q1/48

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L22/12 ,  H01L23/552 ,  H01L23/645 ,  H01L23/66 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01Q1/2283 ,  H01Q1/48 ,  H01L2223/6677 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06531 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

公开(公告)号：US12002349B2

公开(公告)日：2024-06-04

申请号：US17306224

申请日：2021-05-03

Applicant: Alcatel Submarine Networks

Inventor： Mathieu Duval ,  Thierry Verhaege ,  Alain Cordier

IPC: G08C19/00 ,  H03K17/95 ,  H04B3/02 ,  H04B3/26

CPC classification number: G08C19/00 ,  H03K17/952 ,  H04B3/02 ,  H04B3/26 ,  H01L2225/06531

Abstract: In certain embodiments, an assembly has intermediate pods magnetically, but not galvanically, coupled along an electrically conductive cable. Each pod has a magnetic core surrounding and inductively coupled to the cable and one or more coils inductively coupled to the magnetic core. The pod transmits, for example, outgoing current pulses on the cable by inducing electrical signals in the cable using a transmitter coil and the magnetic core. In addition, the pod repeats, for example, incoming current pulses on the cable by inducing electrical signals in the cable using the transmitter coil and the magnetic core, based on electrical signals induced in a receiver coil via the magnetic core by the incoming current pulses. Such an assembly can function as a data collection system for scientific research and/or as an early-warning system for events, such as earthquakes and tsunamis, without having to modify the cable itself.

公开(公告)号：US20240063184A1

公开(公告)日：2024-02-22

申请号：US17889914

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless ,  Owen R. Fay ,  Bang-Ning Hsu

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06551 ,  H01L2225/06586

Abstract: A semiconductor device assembly can include an assembly semiconductor die having a top surface with a first and a second assembly communication element thereat. The semiconductor device assembly can further include a semiconductor die stack coupled to the top surface. The die stack can include a first and a second semiconductor die, each having a top surface perpendicular to the top surface of the assembly semiconductor die. Further, the first semiconductor die can have a first die communication element aligned with and configured to directly communicate with the first assembly communication element, and the second semiconductor die can have a second die communication element aligned with and configured to directly communicate with the second assembly communication element.

公开(公告)号：USRE49773E1

公开(公告)日：2024-01-02

申请号：US17323779

申请日：2021-05-18

Applicant: NANOPAREIL, LLC

Inventor： Todd J. Menkhaus ,  Hao Fong

IPC: B01D39/16 ,  B01D15/32 ,  B01D15/36 ,  B01D15/38 ,  B01J20/24 ,  B01J20/28 ,  B01J20/32 ,  C07K1/22 ,  D01D5/00 ,  D01F2/24 ,  D01F6/44 ,  D01F6/88 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: B01D39/1615 ,  B01D15/327 ,  B01D15/361 ,  B01D15/3809 ,  B01D39/1623 ,  B01D39/1676 ,  B01J20/24 ,  B01J20/28007 ,  B01J20/28038 ,  B01J20/3212 ,  B01J20/3217 ,  B01J20/3248 ,  B01J20/3293 ,  C07K1/22 ,  D01D5/003 ,  D01D5/0007 ,  D01F2/24 ,  D01F6/44 ,  D01F6/88 ,  H01L23/48 ,  H01L24/72 ,  H01L24/73 ,  H01L24/90 ,  H01L24/91 ,  H01L25/0652 ,  H01L25/50 ,  B01D15/3804 ,  B01D2239/025 ,  B01D2239/0414 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/73201 ,  H01L2224/81138 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/157 ,  H01L2924/1579 ,  H01L2924/15153 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/73201 ,  H01L2224/16 ,  H01L2224/72 ,  H01L2224/9211 ,  H01L2224/81 ,  H01L2224/90 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/81138 ,  H01L2924/00012

Abstract: The present invention relates generally to compositions for use in biological and chemical separations, as well as other applications. More specifically, the present invention relates to hybrid felts fabricated from electrospun nanofibers with high permeance and high capacity. Such hybrid felts utilize derivatized cellulose, and at least one non-cellulose-based polymer that may be removed from the felt by subjecting it to moderately elevated temperatures and/or solvents capable of dissolving the non-cellulose-based polymer to leave behind a porous nanofiber felt having more uniform pore sizes and other enhanced properties when compared to single component nanofiber felts.

公开(公告)号：US11817422B2

公开(公告)日：2023-11-14

申请号：US16679180

申请日：2019-11-09

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yohei Igarashi

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/433 ,  H01L23/498 ,  H01L23/36 ,  H01L25/07 ,  H01L49/02

CPC classification number: H01L25/0652 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L25/071 ,  H01L28/10 ,  H01L2224/16238 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06555 ,  H01L2225/06589

Abstract: A semiconductor device includes a first semiconductor element, a first connection terminal formed on a lower surface of the first semiconductor element, a second semiconductor element mounted on the lower surface of the first semiconductor element so that the second semiconductor element partially overlaps the first semiconductor element in plan view, a second connection terminal formed on a lower surface of the second semiconductor element, and a wiring substrate on which the first and second semiconductor elements are mounted. The wiring substrate includes first and second connection pads electrically connected to the first connection terminal and the second connection terminal, respectively. The semiconductor device further includes a third connection terminal formed on the first connection pad and electrically connected to the first connection terminal. One of the first connection terminal and the third connection terminal is a metal post, and the other is a solder ball.

公开(公告)号：US11728315B2

公开(公告)日：2023-08-15

申请号：US17565377

申请日：2021-12-29

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches

IPC: H01L25/065 ,  H01L23/64 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/642 ,  H01L25/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/0557 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.

公开(公告)号：US11705433B2

公开(公告)日：2023-07-18

申请号：US17380653

申请日：2021-07-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/5227 ,  H01L24/32 ,  H01L2224/32145 ,  H01L2225/06531 ,  H01L2225/06544

Abstract: A semiconductor device includes a first semiconductor chip, an adhesive layer that is formed on the first semiconductor chip, and a second semiconductor chip that is arranged on the first semiconductor chip via the adhesive layer. The first semiconductor chip has a first semiconductor substrate and a first wiring layer. The first wiring layer has a first inductor and a first electrode pad. The first wiring layer is formed on the first semiconductor substrate. The second semiconductor chip has a second wiring layer and a second semiconductor substrate. The second wiring layer is formed on the first wiring layer via the adhesive layer. The second semiconductor substrate is formed on the second wiring layer, and has a first opening. In a plan view, the first electrode pad is formed so as not to overlap with the second semiconductor chip, and a second electrode pad overlaps with the first opening.

公开(公告)号：US20190252355A1

公开(公告)日：2019-08-15

申请号：US16391804

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/64

CPC classification number: H01L25/0657 ,  H01L23/642 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.

公开(公告)号：US09922873B2

公开(公告)日：2018-03-20

申请号：US15091990

申请日：2016-04-06

Applicant: GULA CONSULTING LIMITED LIABILITY COMPANY

Inventor： Ernest E. Hollis

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01R43/02 ,  H01L23/50 ,  H01L23/64 ,  H01L23/00 ,  H01L25/00 ,  G02B6/43

CPC classification number: H01L21/76877 ,  G02B6/43 ,  H01L21/76804 ,  H01L23/50 ,  H01L23/5227 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/645 ,  H01L24/03 ,  H01L24/06 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06551 ,  H01L2924/1305 ,  H01L2924/1461 ,  H01L2924/3011 ,  H01R43/0256 ,  H01L2924/00

Abstract: A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias.

公开(公告)号：US09881911B2

公开(公告)日：2018-01-30

申请号：US13801354

申请日：2013-03-13

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani

IPC: H01L23/48 ,  H01L21/60 ,  H05K7/20 ,  H05K1/00 ,  H01L25/11 ,  H01L27/02 ,  H01L21/768 ,  H01L25/065 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00 ,  H01L21/683 ,  H01L25/10 ,  H05K1/18 ,  H01L21/66 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L27/0203 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L22/22 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49833 ,  H01L23/66 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/6677 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/06187 ,  H01L2224/08137 ,  H01L2224/08146 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/14183 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/28105 ,  H01L2224/29024 ,  H01L2224/30183 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73251 ,  H01L2224/82106 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15159 ,  H01L2924/207 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/10515 ,  Y02P70/611 ,  H01L2224/02 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2224/32 ,  H01L2224/19 ,  H01L2924/00

Abstract: An embodiment of an electronic system may be provided so as to have superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in PCBs coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.