公开(公告)号：US09041153B2

公开(公告)日：2015-05-26

申请号：US13248823

申请日：2011-09-29

申请人： Xiangdong Chen ,  Henry Kuo-Shun Chen ,  Wei Xia ,  Bruce Chih-Chieh Shen

发明人： Xiangdong Chen ,  Henry Kuo-Shun Chen ,  Wei Xia ,  Bruce Chih-Chieh Shen

IPC分类号： H01L29/92 ,  H01L23/522 ,  H01L49/02

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.

摘要翻译： 根据一个示例性实施例，在半导体管芯中制造金属 - 绝缘体 - 金属（MIM）电容器的方法包括在位于半导体管芯的第一金属化层下方的器件层上形成底部电容器电极，并形成顶部电容器 形成在底部电容器电极上的层间势垒电介质上的电极。 顶部电容器电极由局部互连金属形成，用于连接器件层中形成的器件。 在一个实施例中，底部电容器电极由栅极金属形成。 该方法还可以包括在第一金属化层中和顶部电容器电极上形成金属板，并将金属板连接到底部电容器电极以提供增加的电容密度。

公开(公告)号：US08847224B2

公开(公告)日：2014-09-30

申请号：US13246710

申请日：2011-09-27

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： H01L29/10 ,  H01L29/732 ,  H01L29/66

CPC分类号： H01L29/66272 ,  H01L29/1004 ,  H01L29/732

摘要： According to one exemplary embodiment, a fin-based bipolar junction transistor (BJT) includes a wide collector situated in a semiconductor substrate. A fin base is disposed over the wide collector. Further, a fin emitter and an epi emitter are disposed over the fin base. A narrow base-emitter junction of the fin-based BJT is formed by the fin base and the fin emitter and the epi emitter provides increased current conduction and reduced resistance for the fin-based BJT. The epi emitter can be epitaxially formed on the fin emitter and can comprise polysilicon. Furthermore, the fin base and the fin emitter can each comprise single crystal silicon.

摘要翻译： 根据一个示例性实施例，鳍式双极结型晶体管（BJT）包括位于半导体衬底中的宽集电极。 翅片底座设置在宽收集器上。 此外，翅片发射极和外延发射极设置在翅片基底之上。 翅片基BJT的窄基极 - 发射极结由翅片基极和鳍发射极形成，并且epi发射极为鳍状BJT提供增加的电流传导和降低的电阻。 外延发射体可以外延形成在鳍发射极上并且可以包括多晶硅。 此外，散热片基板和散热片发射极可以各自包括单晶硅。

公开(公告)号：US08570811B2

公开(公告)日：2013-10-29

申请号：US13219414

申请日：2011-08-26

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： G11C11/34

CPC分类号： H01L29/7855 ,  G11C11/34 ,  G11C17/12 ,  H01L23/5252 ,  H01L27/11206 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a one-time programmable (OTP) device comprises a memory FinFET in parallel with a sensing FinFET. The memory FinFET and the sensing FinFET share a common source region, a common drain region, and a common channel region. The memory FinFET is programmed by having a ruptured gate dielectric, resulting in the sensing FinFET having an altered threshold voltage and an altered drain current. A method for utilizing such an OTP device comprises applying a programming voltage for rupturing the gate dielectric of the memory FinFET thereby achieving a programmed state of the memory FinFET, and detecting by the sensing FinFET the altered threshold voltage and the altered drain current due to the programmed state of the memory FinFET.

摘要翻译： 根据一个实施例，一次性可编程（OTP）器件包括与感测FinFET并联的存储器FinFET。 存储器FinFET和感测FinFET共享共源极区，公共漏极区和公共沟道区。 存储器FinFET通过具有破裂的栅极电介质来编程，导致感测FinFET具有改变的阈值电压和改变的漏极电流。 一种利用这种OTP器件的方法包括施加用于破坏存储器FinFET的栅极电介质的编程电压，从而实现存储器FinFET的编程状态，并且通过感测FinFET检测改变的阈值电压和改变的漏极电流，由于 存储器FinFET的编程状态。

公开(公告)号：US08502320B2

公开(公告)日：2013-08-06

申请号：US13250563

申请日：2011-09-30

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： H01L21/70

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L24/13 ,  H01L24/14 ,  H01L27/0629 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2924/12035 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

公开(公告)号：US08497564B2

公开(公告)日：2013-07-30

申请号：US12583016

申请日：2009-08-13

申请人： Xiangdong Chen ,  Wei Xia

发明人： Xiangdong Chen ,  Wei Xia

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L28/90 ,  H01L29/94 ,  H01L29/945

摘要： According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode.

摘要翻译： 根据示例性实施例，在晶片中制造去耦复合电容器的方法包括覆盖在衬底上的电介质区域包括在电介质区域和衬底中形成贯通晶片通孔。 贯通晶片通孔包括覆盖贯通晶片通孔开口的侧壁和底部的贯通晶片通孔绝缘体，以及通过绝缘体覆盖贯通晶片的贯通晶片通孔导体。 该方法还包括使衬底变薄，形成衬底背面绝缘体，在衬底背面绝缘体中形成开口以通过导体暴露通过晶片，以及通过导体在透晶片上形成背面导体，使得衬底背侧导体 延伸到衬底背面绝缘体上，从而形成去耦复合电容器。 衬底形成第一去耦合复合电容器电极，并且通过晶片通孔导体和衬底背侧导体形成第二去耦复合电容器电极。

公开(公告)号：US20130157843A1

公开(公告)日：2013-06-20

申请号：US13704173

申请日：2011-06-16

申请人： Martin Muhler ,  Wolfgang Schuhmann ,  Wei Xia ,  Michael Bron ,  Justus Masa

发明人： Martin Muhler ,  Wolfgang Schuhmann ,  Wei Xia ,  Michael Bron ,  Justus Masa

IPC分类号： H01M4/90

CPC分类号： H01M4/9008 ,  B01J31/06 ,  B01J2231/62 ,  B82Y30/00 ,  C01B32/00 ,  C01P2002/72 ,  C01P2002/85 ,  C01P2004/64 ,  C01P2006/12 ,  C09C1/56 ,  H01M4/9083 ,  H01M8/083 ,  H01M2004/8689

摘要： This invention relates to a simple method for the synthesis of a highly active metal-free catalyst for oxygen reduction reactions in alkaline media, a catalyst obtainable by said method, an electrode comprising said catalyst and the use of the catalyst and electrode for oxygen reduction reactions in alkaline media.

摘要翻译： 本发明涉及一种用于合成碱性介质中用于氧还原反应的高活性金属催化剂的简单方法，可通过所述方法获得的催化剂，包含所述催化剂的电极以及使用催化剂和电极进行氧还原反应 在碱性介质中。

公开(公告)号：US20130051112A1

公开(公告)日：2013-02-28

申请号：US13219414

申请日：2011-08-26

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： G11C17/08

CPC分类号： H01L29/7855 ,  G11C11/34 ,  G11C17/12 ,  H01L23/5252 ,  H01L27/11206 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a one-time programmable (OTP) device comprises a memory FinFET in parallel with a sensing FinFET. The memory FinFET and the sensing FinFET share a common source region, a common drain region, and a common channel region. The memory FinFET is programmed by having a ruptured gate dielectric, resulting in the sensing FinFET having an altered threshold voltage and an altered drain current. A method for utilizing such an OTP device comprises applying a programming voltage for rupturing the gate dielectric of the memory FinFET thereby achieving a programmed state of the memory FinFET, and detecting by the sensing FinFET the altered threshold voltage and the altered drain current due to the programmed state of the memory FinFET.

摘要翻译： 根据一个实施例，一次性可编程（OTP）器件包括与感测FinFET并联的存储器FinFET。 存储器FinFET和感测FinFET共享共源极区，公共漏极区和公共沟道区。 存储器FinFET通过具有破裂的栅极电介质来编程，导致感测FinFET具有改变的阈值电压和改变的漏极电流。 一种利用这种OTP器件的方法包括施加用于破坏存储器FinFET的栅极电介质的编程电压，从而实现存储器FinFET的编程状态，并且通过感测FinFET检测改变的阈值电压和改变的漏极电流，由于 存储器FinFET的编程状态。

公开(公告)号：US20130009231A1

公开(公告)日：2013-01-10

申请号：US13179248

申请日：2011-07-08

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11534 ,  H01L21/823842

摘要： According to one exemplary embodiment, a method for concurrently fabricating a memory region with a logic region in a common substrate includes forming a lower dielectric segment in the common substrate in the memory and logic regions. The method also includes forming a polysilicon segment over the lower dielectric segment in the memory region, while concurrently forming a sacrificial polysilicon segment over the lower dielectric segment in the logic region. Furthermore, the method includes removing from the logic region the lower dielectric segment and the sacrificial polysilicon segment. The method additionally includes forming a high-k segment in the logic region over the common substrate, and in the memory region over the polysilicon segment and forming a metal segment over the high-k segment in the logic and memory regions. An exemplary structure achieved by the described exemplary method is also disclosed.

摘要翻译： 根据一个示例性实施例，用于同时制造具有公共衬底中的逻辑区域的存储区域的方法包括在存储器和逻辑区域中的公共衬底中形成下部介电段。 该方法还包括在存储器区域中的下介电段上形成多晶硅段，同时在逻辑区域中的下介电段上同时形成牺牲多晶硅段。 此外，该方法包括从逻辑区域去除下介电段和牺牲多晶硅段。 该方法还包括在公共衬底上的逻辑区域中形成高k区段，并在多晶硅区段上的存储区域中形成高k区段，并在逻辑和存储区域中的高k区段上形成金属区段。 还公开了通过描述的示例性方法实现的示例性结构。

公开(公告)号：US08269275B2

公开(公告)日：2012-09-18

申请号：US12589357

申请日：2009-10-21

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US08050076B2

公开(公告)日：2011-11-01

申请号：US12462732

申请日：2009-08-07

申请人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

发明人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/115

摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

摘要翻译： 根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。 可移位阈值电压晶体管具有漏极和栅极短路在一起。 编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。 在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。 在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。 编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。