公开(公告)号：USRE36749E

公开(公告)日：2000-06-27

申请号：US280730

申请日：1994-07-26

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: H04N7/08 ,  H03K5/08 ,  H04L7/04 ,  H04N7/035 ,  H04N7/081 ,  H04N7/083 ,  H04N7/087 ,  H04N7/088 ,  H04N7/04 ,  H04N5/08

CPC classification number: H04L7/046 ,  H03K5/088 ,  H04N7/0355

Abstract: An extractor for digital data transmitted at a first determined frequency (f0) through a video channel after a burst of 0s and 1s emitted at a first frequency (f0). A comparator (1) compares the input signal with a threshold level. A threshold level is provided by an up/down counter (12) operating at a frequency (F0) multiple of the first frequency, the up/down counting input of which is connected to the output of the comparator (1), and a digital/analog converter (16) receiving the output of the up/down counter and supplying the threshold level (V.sub.T).

Abstract translation: 在以第一频率（f0）发射的0和1的脉冲串之后通过视频通道以第一确定频率（f0）发送的数字数据的提取器。 比较器（1）将输入信号与阈值电平进行比较。 阈值电平由上/下计数器（12）提供，该上/下计数器以第一频率的频率（F0）倍工作，其上/下计数输入连接到比较器（1）的输出端，数字 /模拟转换器（16），接收上/下计数器的输出并提供阈值电平（VT）。

公开(公告)号：US6032283A

公开(公告)日：2000-02-29

申请号：US893217

申请日：1997-07-15

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29 ,  G06F11/00

CPC classification number: H03M13/2948 ,  H03M13/151 ,  H03M13/29 ,  H03M13/2915 ,  H03M13/2918 ,  H03M13/293 ,  H03M13/1515 ,  H03M13/152

Abstract: The present invention relates to a method for correcting errors in a data frame including horizontal parity data enabling correction of errors in the rows of the frame based on horizontal syndromes calculated on the rows, and vertical parity data enabling correction of errors in the columns of the frame based on vertical syndromes calculated on the columns. The method includes the steps of calculating, on the fly, the horizontal and vertical syndromes of a current frame on the data of the current frame being received in a slow memory, storing these syndromes in a fast memory area, and, as the data of the next frame are being received in the slow memory, finding the values and positions of the errors of the current frame based on the syndromes stored in the fast memory area.

Abstract translation: 本发明涉及一种用于校正数据帧中的错误的方法，该数据帧包括水平奇偶校验数据，该水平奇偶校验数据使得能够基于在行上计算出的水平校正子校正帧的行中的错误，以及能够修正列中的错误的垂直奇偶校验数据 基于在列上计算的垂直综合征的框架。 该方法包括以下步骤：即时地计算当前帧的水平和垂直综合征对在慢存储器中接收的当前帧的数据，将这些综合征存储在快速存储区域中，并且作为数据 正在慢速存储器中接收下一帧，基于存储在快速存储器区域中的校正子来找出当前帧的错误的值和位置。

公开(公告)号：US5818854A

公开(公告)日：1998-10-06

申请号：US493852

申请日：1995-06-22

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/15 ,  H04B14/04

CPC classification number: H03M13/151

Abstract: A Reed-Solomon decoder receives code sequences of M coefficients having a maximum value N, t of which can be corrected. The Reed-Solomon decoder includes 2t polynomial counters successively receiving the M coefficients of each code sequence, the polynomial counter of rank i (i=0,1 . . . 2t-1), providing the coefficient of the term of degree i of a syndrome polynomial. A circuit provides the coefficients of an error locator polynomial from the coefficients of the syndrome polynomial. Another circuit finds the roots of the error locator polynomial by successively trying values .alpha..sup.1 to .alpha..sup.M. The polynomial counter of rank i is preceded by a multiplier by .alpha..sup.(B+i)(N-M), .alpha..sup.B+i being the i-th root of the code generator polynomial.

Abstract translation: Reed-Solomon解码器接收具有最大值N的M个系数的码序列，其中t可以被校正。 Reed-Solomon解码器包括连续接收每个码序列的M个系数的2t多项式计数器，等级i（i = 0,1 ... 2t-1）的多项式计数器，提供a 综合多项式。 电路根据校正子多项式的系数提供误差定位多项式的系数。 另一个电路通过连续地尝试α1到αM来找出误差定位多项式的根。秩i的多项式计数器之前是α（B + i）（NM）的乘数，αB + i是i- 代码生成器多项式的根。

公开(公告)号：US5802115A

公开(公告)日：1998-09-01

申请号：US697406

申请日：1996-08-23

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: H03M13/23 ,  H03D1/00 ,  G06F11/10 ,  H04L12/50 ,  H04L12/66

CPC classification number: H03M13/23

Abstract: A convolution decoder includes, for each state S of a shift register receiving an initial signal, an add-compare-select circuit which provides a one-bit decision for selecting either one of states 2S or 2S+1 as a state preceding the current state S. A decoding element traces back the memory according to a path indicated by the decisions stored in the memory in order to restore the succession of states of the initial signal. Each calculation cell associated with a state S further includes means for establishing a complex R-bit decision comprising, by decreasing weight, the one-bit decision of the calculation cell and the R-1 most significant bits of the complex decision established by the cell associated with the selected state 2S or 2S+1.

Abstract translation: 卷积解码器包括：对于接收初始信号的移位寄存器的每个状态S，提供用于选择状态2S或2S + 1中的任何一个的一位决定作为当前状态之前的状态的加法比较选择电路 解码元件根据由存储在存储器中的判定指示的路径来跟踪存储器，以恢复初始信号的状态的连续。 与状态S相关联的每个计算单元进一步包括用于建立复杂R位决定的装置，包括通过减小计算单元的一位决定权重和由单元建立的复合决策的R-1最高有效位 与所选择的状态2S或2S + 1相关联。

公开(公告)号：US5502500A

公开(公告)日：1996-03-26

申请号：US54592

申请日：1993-04-29

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: H04N5/08

CPC classification number: H04N5/08

Abstract: A circuit that extracts the synchronization signal from a composite video signal. The circuit includes a stage for aligning the low level of the synchronization signal interval with a reference voltage; a stage for detecting the signal suppression level and a comparator for comparing the aligned video signal with a value intermediate between the low level of the synchronization interval and the signal suppression level. The detecting stage includes a second comparator charging or discharging a capacitor depending on the polarity of the voltage difference across its inputs. The ratio Ic/Id between the values of the charging and discharging currents is selected (approximately equal to 8 in one embodiment) to obtain the suitable value Vsup at the second input of the comparator.

Abstract translation: 从复合视频信号中提取同步信号的电路。 电路包括用于使同步信号间隔的低电平与参考电压对准的级; 用于检测信号抑制电平的级和比较器，用于将对准的视频信号与在同步间隔的低电平和信号抑制电平之间的中间值进行比较。 检测级包括第二比较器，根据其输入端的电压差的极性对电容器进行充电或放电。 选择充电和放电电流值之间的比率Ic / Id（在一个实施例中大约等于8），以在比较器的第二输入端获得合适的值Vsup。

公开(公告)号：USRE30102E

公开(公告)日：1979-09-25

申请号：US885107

申请日：1978-03-09

Applicant: Philippe Thomas ,  Jacques Meyer ,  Jacques M. D'Avigneau

Inventor： Philippe Thomas ,  Jacques Meyer ,  Jacques M. D'Avigneau

IPC: C09D5/03 ,  B27M1/08 ,  B27M3/04 ,  C08K5/12 ,  C08L67/00 ,  C09D167/00

CPC classification number: C09D167/00 ,  C08K5/12 ,  Y10T428/31794

Abstract: The invention relates to compounds based on saturated polyester and cross-linking agent. The compositions comprise a saturated polyester with terminal hydroxyl groups and a cross-linking agent consisting of a dianhydride with ester groups, the product of reaction between a trimellitic anhydride and a diol. Use of the compounds as a binder for powder paints applicable to the automobile, electrical household goods, agricultural machinery and lead industries.

公开(公告)号：US08477876B2

公开(公告)日：2013-07-02

申请号：US13336576

申请日：2011-12-23

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: H04L27/00

CPC classification number: H04L7/027 ,  H04L7/0029 ,  H04L27/0014 ,  H04L27/2657 ,  H04L27/2662 ,  H04L27/2678 ,  H04L2027/0024

Abstract: A method for searching a digital transmission having unknown carrier and symbol frequencies in a modulated reception signal, includes performing successive trials of several carrier and symbol frequencies, using decreasing values of the symbol frequency, demodulating the reception signal with the tried carrier frequency, filtering the demodulated signal in a band having a width corresponding to the currently tried symbol frequency, and producing samples of the filtered signal. For each currently tried symbol frequency, forming a complex indicator having a real component and an imaginary component established from the successive samples of the filtered signal such that they have cyclostationary properties and that one of the components tends to cancel when the other component tends towards a relative maximum, building the spectrum of the variation of the complex indicator, searching for a singular spike in the spectrum, and determining the real symbol frequency from the frequency of the spike.

Abstract translation: 一种在调制接收信号中搜索具有未知载波和符号频率的数字传输的方法，包括使用符号频率的减小值来对多个载波和符号频率进行连续的试验，用所试过的载波频率对接收信号进行解调， 在具有对应于当前尝试的符号频率的宽度的频带中的解调信号，并且产生滤波信号的采样。 对于每个当前尝试的符号频率，形成具有从滤波信号的连续采样建立的实分量和虚分量的复指标，使得它们具有循环平稳特性，并且当另一分量趋于朝向 构建复杂指标变化的频谱，寻找频谱中的奇异峰值，并从尖峰频率确定实数符号频率。

公开(公告)号：US06570936B1

公开(公告)日：2003-05-27

申请号：US09358868

申请日：1999-07-22

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: H04L2722

CPC classification number: H04L27/2273 ,  H04L2027/003 ,  H04L2027/0046

Abstract: A method for estimating the frequency error of a demodulator for restoring two binary signals carried on two carriers of same frequency but in phase quadrature, including the steps of forming vectors having as components the successive couples of values of the two binary signals; applying to each vector a transform which multiplies by four its angle at least when it is equal to a multiple of &pgr;/4 and which substantially preserves its module; and calculating the average of the transformed vectors. The frequency error is obtained as being the derivative of the angle of the average vector.

Abstract translation: 一种用于估计用于恢复在相同频率但相位正交的两个载波上携带的两个二进制信号的解调器的频率误差的方法，包括以下步骤：形成具有两个二进制信号的连续值的分量的矢量; 向每个向量应用至少当其等于pi / 4的倍数并且基本上保持其模块时的四倍角度的变换; 并计算变换矢量的平均值。 获得频率误差为平均矢量角度的导数。

公开(公告)号：US5890800A

公开(公告)日：1999-04-06

申请号：US948741

申请日：1997-10-10

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: G06F7/72 ,  G06F7/00

CPC classification number: G06F7/726

Abstract: Disclosed is a method and a corresponding circuit to compute the result of the division, in a Galois field of 2.sup.n =N elements, of a first number A by a second number B, these numbers being encoded on n bits, wherein said method comprises the following steps:a--the production of a first intermediate number S(1) encoded on n bits by the squaring of the first number A,b--the production of a second intermediate number R(1) encoded on n bits by the multiplication of the intermediate number S(1) by the number B,c--the performance n-2 times of the steps a and b, the intermediate numbers produced by multiplication R(j) being successively squared, and the intermediate numbers produced by squaring S(j) being successively multiplied by the second number B, andd--the production of the result S(n) by the squaring of the intermediate number R(n-1) produced by the �n-1!th multiplication.

Abstract translation: 公开了一种方法和相应的电路，用于在第二数量B的第一数量A的2n = N个元素的伽罗瓦域中计算分割结果，这些数字被编码在n位上，其中所述方法包括 以下步骤：a-通过第一数字A的平方来生成以n位编码的第一中间数S（1），b-通过乘以N位编码的n位编码的第二中间数R（1）的产生 中间数S（1）乘以B，c-步骤a和b的性能n-2次，由乘法R（j）产生的中间数值相继平方，并且通过平方S（ j）依次乘以第二个数字B，d-通过由第[n-1]次乘法产生的中间数R（n-1）的平方而产生结果S（n）。

公开(公告)号：USRE36090E

公开(公告)日：1999-02-09

申请号：US664229

申请日：1996-06-07

Applicant: Jacques Meyer

Inventor： Jacques Meyer

IPC: H03L7/06 ,  H03L7/099 ,  H03L7/10 ,  H03D3/24

CPC classification number: H03L7/0992 ,  H03L7/10

Abstract: A device synchronizes an internal signal with respect to a reference signal, each signal comprising pulses normally occurring at a rated frequency. The device uses a phase comparator to analyze the phase of the internal signal and the reference signal and produce one logic state if the phase of the internal signal is in advance of the phase of the reference signal and a second logic state otherwise. A programmable frequency divider divides an internal clock signal by a first number if the phase comparator signal produces the first logic state or by a second number if the phase comparator produces the second logic state. A multiplexer provides the programmable divider with either the first number or the second number depending on the logic state produced the phase comparator. The device also includes a storage element for sequentially storing a predetermined number of the latest logic states of the phase comparator. The device also includes circuitry for decrementing the first number when the latest stored logic states of the phase comparator have a single occurrence of the first logic state and for incrementing the second number when the latest stored logic states of the phase comparator have a single occurrence of the second state.

Abstract translation: 一个装置相对于参考信号使内部信号同步，每个信号包括通常以额定频率发生的脉冲。 该器件使用相位比较器来分析内部信号和参考信号的相位，并且如果内部信号的相位超出参考信号的相位而产生一个逻辑状态，否则则产生第二逻辑状态。 如果相位比较器信号产生第一逻辑状态，或者相位比较器产生第二逻辑状态，则可编程分频器将内部时钟信号除以第一数字。 复用器根据产生相位比较器的逻辑状态向可编程分频器提供第一数或第二数。 该装置还包括用于顺序存储相位比较器的预定数量的最新逻辑状态的存储元件。 该装置还包括用于当相位比较器的最新存储的逻辑状态具有第一逻辑状态的单次出现时递减第一数量的电路，并且当相位比较器的最新存储的逻辑状态具有单次发生时，增加第二数量 第二个状态。