公开(公告)号：US20100309964A1

公开(公告)日：2010-12-09

申请号：US12809000

申请日：2008-12-19

申请人： Kyung Suk Oh ,  John Wilson ,  Frederick Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

发明人： Kyung Suk Oh ,  John Wilson ,  Frederick Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

IPC分类号： H04B1/38

CPC分类号： G06F13/4243 ,  H04L25/4906 ,  Y02D10/14 ,  Y02D10/151

摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

摘要翻译： 描述通过共享链路在两个设备之间传送双向数据的系统的实施例。 在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。 数据可以在传输之前被编码为一系列并行码字。 每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。 由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。 另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

公开(公告)号：US08588280B2

公开(公告)日：2013-11-19

申请号：US12809000

申请日：2008-12-19

申请人： Kyung Suk Oh ,  John Wilson ,  Frederick A. Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

发明人： Kyung Suk Oh ,  John Wilson ,  Frederick A. Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

IPC分类号： H04B1/38 ,  H04L5/16

CPC分类号： G06F13/4243 ,  H04L25/4906 ,  Y02D10/14 ,  Y02D10/151

摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

摘要翻译： 描述通过共享链路在两个设备之间传送双向数据的系统的实施例。 在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。 数据可以在传输之前被编码为一系列并行码字。 每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。 由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。 另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

公开(公告)号：US20130021857A1

公开(公告)日：2013-01-24

申请号：US13552511

申请日：2012-07-18

申请人： Jade M. Kizer ,  Yoshihiro Koya ,  Frederick A. Ware

发明人： Jade M. Kizer ,  Yoshihiro Koya ,  Frederick A. Ware

IPC分类号： G11C7/00

CPC分类号： G06F13/4239 ,  G11C5/02 ,  G11C5/04 ,  H05K1/0237 ,  H05K1/181 ,  H05K2201/10159 ,  Y02P70/611

摘要： A method of operation in a memory controller comprising generating a mode control signal to specify at least one of a first and second mode is disclosed. In the first mode, the memory controller is configured to operate by issuing a memory access command to initiate a first data transfer between the memory controller and a first memory device, and generating a strobe signal to accompany data associated with the first data transfer. In the second mode, the controller is configured to operate by issuing a memory access command to initiate a second data transfer between the memory controller and at least first and second memory devices involving a full width that includes data widths of both the first and second memory devices, and issuing first and second strobe signals that accompany respective data transfers associated with each of the data widths of the first and second memory devices.

摘要翻译： 公开了一种在存储器控制器中的操作方法，包括生成模式控制信号以指定第一和第二模式中的至少一个。 在第一模式中，存储器控制器被配置为通过发出存储器访问命令来操作，以启动存储器控制器和第一存储器件之间的第一数据传输，并且产生选通信号以伴随与第一数据传输相关联的数据。 在第二模式中，控制器被配置为通过发出存储器访问命令来进行操作，以在存储器控制器与包括全宽度的至少第一和第二存储器件之间的第二数据传输中包括第一和第二存储器的数据宽度 并且发出伴随与第一和第二存储器设备的每个数据宽度相关联的相应数据传输的第一和第二选通信号。

公开(公告)号：US08159887B2

公开(公告)日：2012-04-17

申请号：US12596535

申请日：2008-04-18

申请人： Jade M. Kizer ,  John M. Wilson ,  John Eble, III ,  Frederick A. Ware

发明人： Jade M. Kizer ,  John M. Wilson ,  John Eble, III ,  Frederick A. Ware

IPC分类号： G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

摘要： A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on the results of the sampling, the data strobe and local clock signal are synchronized. In this manner, the data is synchronized to the local clock signal so that sampling of data at the data destination can be performed according to the local clock signal rather than the data strobe.

摘要翻译： 用于同步选通存储器系统10的系统和方法。在存储器读取和/或存储器写入操作期间，根据本地时钟信号71/73在数据目的地50/55处对相应的数据选通进行采样。 基于采样结果，数据选通和本地时钟信号同步。 以这种方式，数据与本地时钟信号同步，使得可以根据本地时钟信号而不是数据选通来执行数据目的地的数据采样。

公开(公告)号：US20100128542A1

公开(公告)日：2010-05-27

申请号：US12598068

申请日：2008-05-08

申请人： Jade M. Kizer ,  Richard E. Perego

发明人： Jade M. Kizer ,  Richard E. Perego

IPC分类号： G11C7/22 ,  H03M9/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  H03L7/0891 ,  H03L7/18

摘要： A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment.

摘要翻译： 存储器系统包括向存储器件发出命令信号和参考时钟信号的存储器控​​制器。 参考时钟信号的边沿速率低于命令信号的比特率，因此存储器件将参考时钟信号相乘以产生用于对输入命令信号进行采样的命令恢复时钟信号。 存储器控制器将命令信号发出为与参考时钟信号的边缘对准的一系列多位命令字，使得存储器件可以使用参考时钟信号的边沿进行命令字对准。

公开(公告)号：US07535271B2

公开(公告)日：2009-05-19

申请号：US11131950

申请日：2005-05-18

申请人： Jade M. Kizer

发明人： Jade M. Kizer

IPC分类号： H03L7/06

CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0814

摘要： A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal.

摘要翻译： 具有时钟保持功能的锁定环路电路。 锁定环电路包括选择电路，相位混合电路，保持信号发生器和锁存电路。 选择电路响应于选择信号选择多个相位值中的一个，并且相位混合电路产生具有根据所选相位值的相位角的第一时钟信号。 保持信号发生器响应于选择信号的转变而置位保持信号，并且锁存电路响应于保持信号的断言而锁存第一时钟信号的状态。

公开(公告)号：US20090089557A1

公开(公告)日：2009-04-02

申请号：US12210104

申请日：2008-09-12

申请人： Lei Luo ,  Frederick A. Ware ,  John Wilson ,  Jade M. Kizer

发明人： Lei Luo ,  Frederick A. Ware ,  John Wilson ,  Jade M. Kizer

IPC分类号： G06F9/22

CPC分类号： G06F9/30018 ,  G09G5/363 ,  G09G5/393 ,  G09G2330/021 ,  G09G2330/06

摘要： Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted.

摘要翻译： 描述在访问存储器期间使用未使用的被屏蔽的数据位的装置的实施例。 该装置包括选择电路，其选择在访问存储器期间在数据线上驱动的数据位。 该选择电路包括接收数据屏蔽信号的控制输入，该数据屏蔽信号指示在访问存储器期间是否要屏蔽一组数据位。 在访问存储器期间，当数据屏蔽信号未被置位时，选择电路选择要驱动的一组数据位，或者当数据屏蔽信号被断言时要选择要驱动的一组值。

公开(公告)号：US06922091B2

公开(公告)日：2005-07-26

申请号：US10374615

申请日：2003-02-25

申请人： Jade M. Kizer

发明人： Jade M. Kizer

IPC分类号： G06F1/10 ,  H03L7/07 ,  H03L7/081 ,  H03L7/06

CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0814

摘要： A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal.

摘要翻译： 具有时钟保持功能的锁定环路电路。 锁定环电路包括选择电路，相位混合电路，保持信号发生器和锁存电路。 选择电路响应于选择信号选择多个相位值中的一个，并且相位混合电路产生具有根据所选相位值的相位角的第一时钟信号。 保持信号发生器响应于选择信号的转变而置位保持信号，并且锁存电路响应于保持信号的断言而锁存第一时钟信号的状态。

公开(公告)号：US08441872B2

公开(公告)日：2013-05-14

申请号：US13552511

申请日：2012-07-18

申请人： Jade M. Kizer ,  Yoshihito Koya ,  Frederick A. Ware

发明人： Jade M. Kizer ,  Yoshihito Koya ,  Frederick A. Ware

IPC分类号： G11C7/00

CPC分类号： G06F13/4239 ,  G11C5/02 ,  G11C5/04 ,  H05K1/0237 ,  H05K1/181 ,  H05K2201/10159 ,  Y02P70/611

摘要： A method of operation in a memory controller comprising generating a mode control signal to specify at least one of a first and second mode is disclosed. In the first mode, the memory controller is configured to operate by issuing a memory access command to initiate a first data transfer between the memory controller and a first memory device, and generating a strobe signal to accompany data associated with the first data transfer. In the second mode, the controller is configured to operate by issuing a memory access command to initiate a second data transfer between the memory controller and at least first and second memory devices involving a full width that includes data widths of both the first and second memory devices, and issuing first and second strobe signals that accompany respective data transfers associated with each of the data widths of the first and second memory devices.

摘要翻译： 公开了一种在存储器控制器中的操作方法，包括生成模式控制信号以指定第一和第二模式中的至少一个。 在第一模式中，存储器控制器被配置为通过发出存储器访问命令来操作，以启动存储器控制器和第一存储器件之间的第一数据传输，并且产生选通信号以伴随与第一数据传输相关联的数据。 在第二模式中，控制器被配置为通过发出存储器访问命令来进行操作，以在存储器控制器与包括全宽度的至少第一和第二存储器件之间的第二数据传输中包括第一和第二存储器的数据宽度 并且发出伴随与第一和第二存储器设备的每个数据宽度相关联的相应数据传输的第一和第二选通信号。

公开(公告)号：US08295118B2

公开(公告)日：2012-10-23

申请号：US12721520

申请日：2010-03-10

申请人： Scott C. Best ,  Jade M. Kizer

发明人： Scott C. Best ,  Jade M. Kizer

IPC分类号： G11C8/00

CPC分类号： G06F13/4059

摘要： A method is disclosed comprising detecting an edge-transition of a strobe signal using hysteresis, the strobe signal originating in a first clock domain. A count is controlled in a first direction in response to the detected edge-transition. The count is controlled in a second direction in response to an edge-transition of a clock signal, the clock signal originating in a second clock domain. Data is interfaced between the first and second clock domains in response to the count.

摘要翻译： 公开了一种方法，包括使用滞后来检测选通信号的边沿转变，该选通信号源自第一时钟域。 响应于检测到的边缘转变，计数在第一方向上被控制。 响应于时钟信号的边沿转换，计数被控制在第二方向上，时钟信号源自第二时钟域。 响应于计数，数据在第一和第二时钟域之间接口。