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    Self-timed interface for strobe-based systems
    1.
    发明授权
    Self-timed interface for strobe-based systems 有权
    用于基于频闪的系统的自定义接口

    公开(公告)号：US08295118B2

    公开(公告)日：2012-10-23

    申请号：US12721520

    申请日：2010-03-10

    申请人： Scott C. Best ,  Jade M. Kizer

    发明人： Scott C. Best ,  Jade M. Kizer

    IPC分类号： G11C8/00

    CPC分类号： G06F13/4059

    摘要： A method is disclosed comprising detecting an edge-transition of a strobe signal using hysteresis, the strobe signal originating in a first clock domain. A count is controlled in a first direction in response to the detected edge-transition. The count is controlled in a second direction in response to an edge-transition of a clock signal, the clock signal originating in a second clock domain. Data is interfaced between the first and second clock domains in response to the count.

    摘要翻译： 公开了一种方法，包括使用滞后来检测选通信号的边沿转变，该选通信号源自第一时钟域。 响应于检测到的边缘转变，计数在第一方向上被控制。 响应于时钟信号的边沿转换，计数被控制在第二方向上，时钟信号源自第二时钟域。 响应于计数，数据在第一和第二时钟域之间接口。

    Self-timed interface for strobe-based systems
    2.
    发明授权
    Self-timed interface for strobe-based systems 有权
    用于基于频闪的系统的自定义接口

    公开(公告)号：US07688672B2

    公开(公告)日：2010-03-30

    申请号：US11080613

    申请日：2005-03-14

    申请人： Scott C. Best ,  Jade M. Kizer

    发明人： Scott C. Best ,  Jade M. Kizer

    IPC分类号： G11C8/00

    CPC分类号： G06F13/4059

    摘要： Self-timed interfaces and methods for interfacing different timing domains. These self-timed interfaces receive a strobe signal from a component operating under a first clock domain. A first signal path of the self-timed interface couples the strobe signal to a receiver that samples data of data line under control of the strobe signal. A second signal path of the self-timed interface couples the strobe signal to an interface circuit through a hysteresis-based element. The interface circuit, under control of an output of the hysteresis-based element along with a clock signal that originates under a second clock domain, generates an interface enable signal for use in controlling data transfers between the different clock domains.

    摘要翻译： 用于连接不同定时域的自定义接口和方法。 这些自定时接口从在第一时钟域下运行的组件接收选通信号。 自定时接口的第一信号路径将选通信号耦合到在选通信号的控制下采样数据线的数据的接收机。 自定时接口的第二信号路径通过基于滞后的元件将选通信号耦合到接口电路。 接口电路在基于滞后的元件的输出的控制下以及起始于第二时钟域的时钟信号产生用于控制不同时钟域之间的数据传输的接口使能信号。

    SELF-TIMED INTERFACE FOR STROBE-BASED SYSTEMS
    3.
    发明申请
    SELF-TIMED INTERFACE FOR STROBE-BASED SYSTEMS 有权
    用于基于STROBE的系统的自定义接口

    公开(公告)号：US20100254204A1

    公开(公告)日：2010-10-07

    申请号：US12721520

    申请日：2010-03-10

    申请人： Scott C. Best ,  Jade M. Kizer

    发明人： Scott C. Best ,  Jade M. Kizer

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G06F13/4059

    摘要： A method is disclosed comprising detecting an edge-transition of a strobe signal using hysteresis, the strobe signal originating in a first clock domain. A count is controlled in a first direction in response to the detected edge-transition. The count is controlled in a second direction in response to an edge-transition of a clock signal, the clock signal originating in a second clock domain. Data is interfaced between the first and second clock domains in response to the count.

    摘要翻译： 公开了一种方法，包括使用滞后来检测选通信号的边沿转变，该选通信号源自第一时钟域。 响应于检测到的边缘转变，计数在第一方向上被控制。 响应于时钟信号的边沿转换，计数被控制在第二方向上，时钟信号源自第二时钟域。 响应于计数，数据在第一和第二时钟域之间接口。

    Memory controller for strobe-based memory systems
    5.
    发明授权
    Memory controller for strobe-based memory systems 有权
    内存控制器，用于基于闪光灯的内存系统

    公开(公告)号：US08743635B2

    公开(公告)日：2014-06-03

    申请号：US13416905

    申请日：2012-03-09

    申请人： Jade M. Kizer ,  Sivakumar Doraiswamy ,  Benedict Lau

    发明人： Jade M. Kizer ,  Sivakumar Doraiswamy ,  Benedict Lau

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4076 ,  G06F13/1689 ,  G06F13/405 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4096

    摘要： A memory controller for strobe-based memory systems is disclosed. The memory controller includes a circuit to generate a control signal having a predetermined timing relationship with respect to a first clock signal, a circuit to receive the control signal, and a receiver to sample the read data in response to the qualified read strobe signal. The receiving circuit includes an input to receive an external read strobe signal transmitted by a semiconductor memory device, circuitry to synchronize the control signal and the received read strobe signal to have a common timing relationship with respect to each other, and circuitry to gate the read strobe signal based on the synchronized control signal.

    摘要翻译： 公开了一种用于基于闪光灯的存储器系统的存储器控​​制器。 存储器控制器包括用于产生相对于第一时钟信号具有预定定时关系的控制信号的电路，用于接收控制信号的电路，以及响应于限定读选通信号对读数据进行采样的接收器。 接收电路包括用于接收由半导体存储器件发送的外部读取选通信号的输入端，用于使控制信号和接收的读取选通信号同步以具有相对于彼此的公共定时关系的电路， 基于同步控制信号的选通信号。

    Utilizing masked data bits during accesses to a memory
    6.
    发明授权
    Utilizing masked data bits during accesses to a memory 有权
    在访问存储器期间利用屏蔽的数据位

    公开(公告)号：US08581920B2

    公开(公告)日：2013-11-12

    申请号：US12210104

    申请日：2008-09-12

    申请人： Lei Luo ,  Frederick A. Ware ,  John Wilson ,  Jade M. Kizer

    发明人： Lei Luo ,  Frederick A. Ware ,  John Wilson ,  Jade M. Kizer

    IPC分类号： G09G5/37 ,  G06T1/60

    CPC分类号： G06F9/30018 ,  G09G5/363 ,  G09G5/393 ,  G09G2330/021 ,  G09G2330/06

    摘要： Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted.

    摘要翻译： 描述在访问存储器期间使用未使用的被屏蔽的数据位的装置的实施例。 该装置包括选择电路，其选择在访问存储器期间在数据线上驱动的数据位。 该选择电路包括接收数据屏蔽信号的控制输入，该数据屏蔽信号指示在访问存储器期间是否要屏蔽一组数据位。 在访问存储器期间，当数据屏蔽信号未被置位时，选择电路选择要驱动的一组数据位，或者当数据屏蔽信号被断言时要选择要驱动的一组值。

    Reference clock and command word alignment
    7.
    发明授权
    Reference clock and command word alignment 有权
    参考时钟和命令字对齐

    公开(公告)号：US08352772B2

    公开(公告)日：2013-01-08

    申请号：US12598068

    申请日：2008-05-08

    申请人： Jade M. Kizer ,  Richard E. Perego

    发明人： Jade M. Kizer ,  Richard E. Perego

    IPC分类号： G06F1/04 ,  G06F1/14 ,  G06F11/00

    CPC分类号： G11C7/22 ,  G11C7/222 ,  H03L7/0891 ,  H03L7/18

    摘要： A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment.

    摘要翻译： 存储器系统包括向存储器件发出命令信号和参考时钟信号的存储器控​​制器。 参考时钟信号的边沿速率低于命令信号的比特率，因此存储器件将参考时钟信号相乘以产生用于对输入的命令信号进行采样的命令恢复时钟信号。 存储器控制器将命令信号发出为与参考时钟信号的边缘对准的一系列多位命令字，使得存储器件可以使用参考时钟信号的边沿进行命令字对准。

    ASYMMETRIC COMMUNICATION ON SHARED LINKS
    9.
    发明申请
    ASYMMETRIC COMMUNICATION ON SHARED LINKS 有权
    共享链路上的不对称通信

    公开(公告)号：US20100309964A1

    公开(公告)日：2010-12-09

    申请号：US12809000

    申请日：2008-12-19

    申请人： Kyung Suk Oh ,  John Wilson ,  Frederick Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

    发明人： Kyung Suk Oh ,  John Wilson ,  Frederick Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

    IPC分类号： H04B1/38

    CPC分类号： G06F13/4243 ,  H04L25/4906 ,  Y02D10/14 ,  Y02D10/151

    摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

    摘要翻译： 描述通过共享链路在两个设备之间传送双向数据的系统的实施例。 在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。 数据可以在传输之前被编码为一系列并行码字。 每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。 由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。 另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

    Method and apparatus for programmable sampling clock edge selection
    10.
    发明授权
    Method and apparatus for programmable sampling clock edge selection 有权
    用于可编程采样时钟沿选择的方法和装置

    公开(公告)号：US07275171B2

    公开(公告)日：2007-09-25

    申请号：US10443297

    申请日：2003-05-22

    申请人： Jade M. Kizer ,  Benedict C. Lau ,  Bradley A. May

    发明人： Jade M. Kizer ,  Benedict C. Lau ,  Bradley A. May

    IPC分类号： H04L7/00

    CPC分类号： G06F1/12

    摘要： A method and apparatus for transferring data across a clock domain boundary is described. In one embodiment, a fixed relationship between a faster clock and a slower clock is maintained in the process of phase alignment to allow great flexibility in allowable combinations of slower clock and faster clock frequencies. In one embodiment, an encoded edge select word is generated once at system initialization and used thereafter to select edges of the faster clock on which to sample data that comes from the clock domain of the slower clock. The value of the encoded edge select word is based, in part, on the fixed relationship between the faster clock and the slower clock.

    摘要翻译： 描述了用于在时钟域边界上传送数据的方法和装置。 在一个实施例中，在相位对准的过程中保持较快时钟和较慢时钟之间的固定关系，以允许较慢时钟和较快时钟频率的可允许组合中的较大灵活性。 在一个实施例中，编码边缘选择字在系统初始化时产生一次，并且此后使用其选择在其上采样来自较慢时钟的时钟域的数据的较快时钟的边沿。 编码边缘选择字的值部分地基于较快时钟和较慢时钟之间的固定关系。