公开(公告)号：US20120132976A1

公开(公告)日：2012-05-31

申请号：US13368556

申请日：2012-02-08

Applicant: Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

Inventor： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

IPC: H01L29/788 ,  H01L29/06

CPC classification number: H01L21/76229

Abstract: A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

Abstract translation: 提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。 半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。 电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。 芯绝缘材料层具有比填充绝缘材料层更大的流动性。

公开(公告)号：US08187935B2

公开(公告)日：2012-05-29

申请号：US12795025

申请日：2010-06-07

Applicant: Young-Ho Lee ,  Keon-Soo Kim ,  Jae-Hwang Sim ,  Jin-Hyun Shin ,  Kyung-Hoon Min

Inventor： Young-Ho Lee ,  Keon-Soo Kim ,  Jae-Hwang Sim ,  Jin-Hyun Shin ,  Kyung-Hoon Min

IPC: H01L21/8247

CPC classification number: H01L21/76229 ,  H01L21/823481 ,  H01L27/1052

Abstract: A method of forming an active region structure includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region, forming upper cell mask patterns having a line shape in the cell array region, forming first and second peripheral mask patterns in the peripheral circuit region, the first and second peripheral mask patterns being stacked in sequence and covering the peripheral circuit region, and upper surfaces of the upper cell mask patterns forming a step difference with an upper surface of the second peripheral mask pattern, forming spacers on sidewalls of the upper cell mask patterns to expose lower portions of the upper cell mask patterns and the second peripheral mask pattern, and removing the lower portions of the upper cell mask patterns using the spacers and the first and second peripheral mask patterns as an etch mask.

Abstract translation: 形成有源区域结构的方法包括制备具有单元阵列区域和外围电路区域的半导体衬底，在单元阵列区域中形成具有线状的上层单元掩模图案，在外围电路中形成第一和第二外围掩模图案 区域，第一外围掩模图案和第二外围掩模图案依次堆叠并覆盖外围电路区域，并且上部单元掩模图案的上表面与第二外围掩模图案的上表面形成阶梯差，在第二外围掩模图案的侧壁上形成间隔物 上部单元掩模图案以暴露上部单元掩模图案和第二外围掩模图案的下部，并且使用间隔件和第一外围掩模图案和第二外围掩模图案作为蚀刻掩模去除上部单元掩模图案的下部。

公开(公告)号：US20110227231A1

公开(公告)日：2011-09-22

申请号：US13111100

申请日：2011-05-19

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

IPC: H01L23/48

CPC classification number: H01L21/76816 ,  H01L21/31144

Abstract: A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.

Abstract translation: 半导体器件可以包括以锯齿形图案布置的插塞，电连接到插头的互连和插入在插头和互连之间的保护图案以选择性地暴露插头。 互连可以包括与由保护图案选择性地暴露的插头接触的连接部分。 制造半导体器件的方法包括：在形成模制图案和掩模图案之后，使用掩模图案选择性地蚀刻保护层以形成露出插头的保护图案。

公开(公告)号：US07968447B2

公开(公告)日：2011-06-28

申请号：US12465013

申请日：2009-05-13

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

IPC: H01L21/4763

CPC classification number: H01L21/76816 ,  H01L21/31144

Abstract: A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.

Abstract translation: 半导体器件可以包括以锯齿形图案布置的插塞，电连接到插头的互连和插入在插头和互连之间的保护图案以选择性地暴露插头。 互连可以包括与由保护图案选择性地暴露的插头接触的连接部分。 制造半导体器件的方法包括：在形成模制图案和掩模图案之后，使用掩模图案选择性地蚀刻保护层以形成露出插头的保护图案。

公开(公告)号：US20110062508A1

公开(公告)日：2011-03-17

申请号：US12882436

申请日：2010-09-15

Applicant: Yoonmoon PARK ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

Inventor： Yoonmoon PARK ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

IPC: H01L29/788

CPC classification number: H01L27/11531 ,  H01L27/11526 ,  H01L28/20 ,  H01L28/24

Abstract: Embodiments of a semiconductor device including a resistor and a method of fabricating the same are provided. The semiconductor device includes a mold pattern disposed on a semiconductor substrate to define a trench, a resistance pattern including a body region and first and second contact regions, wherein the body region covers the bottom and sidewalls of the trench, the first and second contact regions extend from the extending from the body region over upper surfaces of the mold pattern, respectively; and first and second lines contacting the first and second contact regions, respectively.

Abstract translation: 提供了包括电阻器的半导体器件及其制造方法的实施例。 半导体器件包括设置在半导体衬底上以限定沟槽的模具图案，包括主体区域和第一和第二接触区域的电阻图案，其中主体区域覆盖沟槽的底部和侧壁，第一和第二接触区域 分别从模具图案的上表面上的身体区域延伸出来; 以及分别与第一和第二接触区域接触的第一和第二线路。

公开(公告)号：US20100096719A1

公开(公告)日：2010-04-22

申请号：US12418023

申请日：2009-04-03

Applicant: Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

Inventor： Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

IPC: H01L29/06 ,  H01L21/762 ,  H01L23/544

CPC classification number: H01L27/0207 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are isotropically etched to remove the etch mask pattern from the first mask structure while maintaining at least a portion of the etch mask pattern on the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region using the portion of the etch mask pattern on the second mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. The feature layer may be patterned using the first mask pattern as a mask to define a first feature on the first region, and using the second mask pattern as a mask to define a second feature on the second region having a greater width than the first feature.

Abstract translation: 制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。 第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。 各向同性蚀刻第一和第二掩模结构的蚀刻掩模图案以从第一掩模结构去除蚀刻掩模图案，同时将蚀刻掩模图案的至少一部分保持在第二掩模结构上。 间隔件形成在第一和第二掩模结构的相对侧壁上。 使用第二掩模结构上的蚀刻掩模图案的部分作为掩模，第一掩模结构从第一区域中的间隔物之间​​选择性地移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物 以及第二掩模图案，其包括在第二区域中具有第二掩模结构的相对的侧壁间隔物。 可以使用第一掩模图案作为掩模来对特征层进行图案化，以在第一区域上限定第一特征，并且使用第二掩模图案作为掩模来限定具有比第一特征宽的宽度的第二区域上的第二特征 。

公开(公告)号：US07611948B2

公开(公告)日：2009-11-03

申请号：US11945477

申请日：2007-11-27

Applicant: Jae-Hwang Sim ,  Yong-Sik Yim ,  Ki-Nam Kim ,  Jae-Kwan Park

Inventor： Jae-Hwang Sim ,  Yong-Sik Yim ,  Ki-Nam Kim ,  Jae-Kwan Park

IPC: H01L21/8247 ,  H01L21/8222

CPC classification number: H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  Y10S438/954

Abstract: A method of forming a non-volatile memory device includes forming first mask patterns, which can have relatively large distances therebetween. A distance regulating layer is formed that conformally covers the first mask patterns. Second mask patterns are formed in grooves on the distance regulating layer between the first mask patterns.

Abstract translation: 形成非易失性存储器件的方法包括形成第一掩模图案，它们之间的距离可以相对较大。 形成保形地覆盖第一掩模图案的距离调节层。 在第一掩模图案之间的距离调节层的凹槽中形成第二掩模图案。

公开(公告)号：US20080227258A1

公开(公告)日：2008-09-18

申请号：US12074992

申请日：2008-03-07

Applicant: Sang-Yong Park ,  Sung-Hyun Kwon ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Jae-Kwan Park

Inventor： Sang-Yong Park ,  Sung-Hyun Kwon ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Jae-Kwan Park

IPC: H01L21/336 ,  H01L21/31

CPC classification number: H01L27/11521 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/11524 ,  H01L27/11568

Abstract: Methods of forming a semiconductor device include forming a mask layer on a semiconductor substrate. The mask layer has vertically and horizontally extending portions. The vertically extending portions have a thickness selected to provide a desired line width to an underlying structure to be formed using the mask layer and a height greater than a height of the horizontally extending portions. The underlying structure is formed using the mask layer.

Abstract translation: 形成半导体器件的方法包括在半导体衬底上形成掩模层。 掩模层具有垂直和水平延伸的部分。 垂直延伸部分具有选择的厚度，以使要使用掩模层形成的下层结构和高于水平延伸部分的高度的高度提供期望的线宽。 使用掩模层形成底层结构。

公开(公告)号：US09761603B2

公开(公告)日：2017-09-12

申请号：US14964624

申请日：2015-12-10

Applicant: Min-Sung Song ,  Jae-Hwang Sim ,  Joon-Sung Lim

Inventor： Min-Sung Song ,  Jae-Hwang Sim ,  Joon-Sung Lim

IPC: H01L21/4763 ,  H01L27/11573 ,  H01L21/311 ,  H01L27/11526 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L27/11573 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/11526

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

公开(公告)号：US09041088B2

公开(公告)日：2015-05-26

申请号：US14339762

申请日：2014-07-24

Applicant: Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

IPC: H01L29/06 ,  H01L21/764 ,  H01L29/788 ,  H01L27/115 ,  H01L21/762

CPC classification number: H01L27/11521 ,  H01L21/76289 ,  H01L21/764 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11563 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7881

Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

Abstract translation: 公开了非易失性存储器件及其制造方法。 非易失性存储器件包括限定衬底中的有源部分和设置在衬底上的栅极结构的器件隔离图案。 有源部分在第一方向上彼此间隔开，并且在垂直于第一方向的第二方向上延伸。 栅极结构在第二方向上彼此间隔开并且在第一方向上延伸。 每个器件隔离图案包括第一气隙，并且第一气隙的顶表面和底表面中的每一个在沿着第二方向截取的截面图中具有波形。