公开(公告)号：US07937568B2

公开(公告)日：2011-05-03

申请号：US11776121

申请日：2007-07-11

申请人： Anthony Correale, Jr. ,  Kenichi Tsuchiya

发明人： Anthony Correale, Jr. ,  Kenichi Tsuchiya

IPC分类号： G06F9/30 ,  G06F9/302

CPC分类号： G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/3836 ,  G06F9/3869 ,  Y02D10/126

摘要： A method, system and processor for increasing the instruction throughput in a processor executing longer latency instructions within the instruction pipeline. Logic associated with specific stages of the execution pipeline, responsible for executing the particular type of instructions, determines when at least a threshold number of the particular-type instructions is scheduled to be executed. The logic then automatically changes an execution cycle frequency of the specific pipeline stages from a first cycle frequency to a second, pre-established higher cycle frequency, which enables more efficient execution and higher execution throughput of the particular-type instructions. The cycle frequency of only the one or more functional stages are switched to the higher cycle frequency independent of the cycle frequency of the other functional stages in the processor pipeline. The logic also automatically switches the execution cycle frequency of the specific pipeline stages back from the second, higher cycle frequency to the first cycle frequency, when the number of scheduled first-type instructions has completed execution.

摘要翻译： 一种用于增加处理器中的指令吞吐量的方法，系统和处理器，其执行指令流水线内的较长延迟指令。 与执行流水线的特定阶段相关联的逻辑负责执行特定类型的指令，确定何时调度执行特定类型指令的至少一个阈值数目。 逻辑然后自动地将特定流水线级的执行周期频率​​从第一周期频率改变到第二预先建立的较高周期频率，这使得能够更有效地执行特定类型指令的执行吞吐量。 只有一个或多个功能级的周期频率被切换到与处理器管线中的其他功能级的周期频率无关的较高周期频率。 当调度的第一类型指令的数量已经完成执行时，逻辑还自动将特定流水线级的执行周期频率​​从第二较高周期频率切换到第一周期频率。

公开(公告)号：US20090019265A1

公开(公告)日：2009-01-15

申请号：US11776222

申请日：2007-07-11

申请人： ANTHONY CORREALE, JR. ,  Kenichi Tsuchiya

发明人： ANTHONY CORREALE, JR. ,  Kenichi Tsuchiya

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3296 ,  G06F9/30145 ,  G06F9/3869 ,  Y02D10/126 ,  Y02D10/172

摘要： A method, system and processor for adaptively and selectively controlling the instruction execution frequency of a data processor. Processing logic or a software compiler determines when a number of first-type instructions, requiring longer execution latency, are scheduled to be executed. The logic/compiler then triggers the CPM unit to automatically switch the execution frequency of the instruction processor from a first frequency that is optimal for processing regular-type instructions to a second, pre-established lower frequency that is optimal for processing the first-type instructions, to enable more efficient execution and higher execution throughput of the number of first-type operations within the processor. When the first-type instructions have completed execution, the processor's instruction execution frequency is returned to the first optimal frequency.

摘要翻译： 一种用于自适应地和选择性地控制数据处理器的指令执行频率的方法，系统和处理器。 处理逻辑或软件编译器确定何时调度执行需要更长执行延迟的第一类指令。 逻辑/编译器然后触发CPM单元自动地将指令处理器的执行频率从处理规则类型指令的最佳的第一频率切换到对于处理第一类型的处理最佳的第二预先建立的较低频率 指令，以实现处理器内第一类型操作数量的更高效的执行和更高的执行吞吐量。 当第一类指令完成执行时，处理器的指令执行频率返回到第一最佳频率。

公开(公告)号：US20080320236A1

公开(公告)日：2008-12-25

申请号：US11767882

申请日：2007-06-25

申请人： Makoto Ueda ,  Kenichi Tsuchiya ,  Takeo Nakada ,  Norio Fujita

发明人： Makoto Ueda ,  Kenichi Tsuchiya ,  Takeo Nakada ,  Norio Fujita

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0811 ,  G06F12/0813

摘要： A system includes processor units, caches, memory shared by the processor units, a system bus interface, and a cache snoop interfaces. Each processor unit has one of the caches. The system bus interface communicatively connects the processor units to the memory via at least the caches, and is a non-cache snoop system bus interface. The cache snoop interface communicatively connects the caches, and is independent of the system bus interface. Upon a given processor unit writing a new value to an address within the memory such that the new value and the address are cached within the cache of the given processor unit a write invalidation event is sent over the cache snoop interface to the caches of the processor units other than the given processor unit. This event invalidates the address as stored within any of the caches other than the cache of the given processor unit.

摘要翻译： 系统包括处理器单元，高速缓存，由处理器单元共享的存储器，系统总线接口和高速缓存监听接口。 每个处理器单元都有一个高速缓存。 系统总线接口至少通过高速缓存通信地将处理器单元连接到存储器，并且是非高速缓存监听系统总线接口。 缓存监听接口通信地连接高速缓存，并且独立于系统总线接口。 在给定处理器单元向存储器中的地址写入新值使得新值和地址被缓存在给定处理器单元的高速缓存内时，写无效事件通过高速缓存侦听接口发送到处理器的高速缓存 单位除了给定的处理器单位。 该事件将存储在除了给定处理器单元的高速缓存之外的任何高速缓存中的地址无效。

公开(公告)号：US20080022044A1

公开(公告)日：2008-01-24

申请号：US11835519

申请日：2007-08-08

申请人： Nathan Nunamaker ,  Jack Randolph ,  Kenichi Tsuchiya

发明人： Nathan Nunamaker ,  Jack Randolph ,  Kenichi Tsuchiya

IPC分类号： G06F12/00

CPC分类号： G06F9/30138 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3851 ,  G06F9/3861 ,  G06F12/0875

摘要： A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Selection logic enables selecting output of either register bank for input to processor execution logic. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.

摘要翻译： 处理器包含具有不同访问延迟的多级寄存器。 相对较小的寄存器集合包含在相对较快的较高级别的寄存器组中，并且较大的更完整的寄存器集合包含在相对较慢的较低级别的寄存器组中。 在物理上，较高级别的寄存器组被放置得更接近从寄存器接收输入的功能逻辑。 选择逻辑使能选择任一寄存器组的输出，以输入到处理器执行逻辑。 优选地，下级存储体包括一整套所有处理器寄存器，并且较高级存储体包括较小的寄存器子集，复制下级存储体中的信息。 较高级别的存储体优选在单个时钟周期内可访问。

公开(公告)号：US06918866B2

公开(公告)日：2005-07-19

申请号：US10633910

申请日：2003-08-04

申请人： Shiro Miyamori ,  Yasuyuki Hayasaki ,  Masanari Umeda ,  Kenichi Tsuchiya

发明人： Shiro Miyamori ,  Yasuyuki Hayasaki ,  Masanari Umeda ,  Kenichi Tsuchiya

IPC分类号： G03G15/00 ,  C08K3/36 ,  C08L9/02 ,  C08L21/00 ,  C08L71/03 ,  F16C13/00 ,  G03G15/02 ,  G03G15/08 ,  G03G15/16

CPC分类号： G03G15/0233 ,  G03G2215/0634 ,  G03G2215/1614 ,  Y10T428/31826

摘要： An electrically conductive roll includes a shaft body and at least a conductive elastic layer formed by extrusion on an outer circumferential surface of the shaft body. The conductive elastic layer is formed from at least one conductive rubber composition which includes a rubber material, a thermoplastic resin having crosslinkable double bonds and a melting point in a range from 40° C. to 100° C., and at least one conductive agent. The thermoplastic resin is included in an amount of 5 to 50 wt. % of a total amount of the rubber material and the thermoplastic resin.

摘要翻译： 导电辊包括轴体和至少一个通过在轴体的外圆周表面上挤压形成的导电弹性层。 导电弹性层由至少一种导电橡胶组合物形成，该组合物包括橡胶材料，具有可交联双键的热塑性树脂和熔点在40℃至100℃的范围内，以及至少一种导电剂 。 热塑性树脂的含量为5〜50重量％。 橡胶材料和热塑性树脂的总量的百分比。

公开(公告)号：US06179040B2

公开(公告)日：2001-01-30

申请号：US09198453

申请日：1998-11-24

申请人： Tomohiro Aoki ,  Masami Kawasaki ,  Kenichi Tsuchiya

发明人： Tomohiro Aoki ,  Masami Kawasaki ,  Kenichi Tsuchiya

IPC分类号： B22D1708

CPC分类号： F16H63/32 ,  F16H2063/324 ,  Y10S164/90

摘要： A shift fork used in a transmission which engages with an engaging groove of a coupling sleeve of the transmission, comprises a fork main body and an engaging part integrally molded therewith. The engaging part has an engaging surface which comes in contact with a coupling sleeve, and the engaging surface is formed in a bulging shape by high precision aluminum diecasting.

摘要翻译： 用于与变速器的联接套筒的接合槽接合的变速器中的换档拨叉包括叉主体和与其一体成型的接合部。 接合部具有与联接套接触的接合面，并且通过高精度铝压铸形成凸出形状的接合面。

公开(公告)号：US5950994A

公开(公告)日：1999-09-14

申请号：US979184

申请日：1997-11-26

申请人： Nobuyuki Hosoya ,  Kenichi Tsuchiya ,  Masaaki Sonoda

发明人： Nobuyuki Hosoya ,  Kenichi Tsuchiya ,  Masaaki Sonoda

IPC分类号： B60K5/12 ,  F16F13/10 ,  F16F13/18 ,  F16F5/00

CPC分类号： F16F13/108

摘要： A vibration isolating apparatus includes a first mounting member; a second mounting member having a through hole; an elastic body provided to be elastically deformable and mounted in such a manner as to be interposed between the first mounting member and the second mounting member; a liquid chamber of which at least a portion of a partition wall is formed of the elastic body and the second mounting member and which is filled with a liquid; and an elastic membrane provided to be elastically deformable and fixed to a portion of the second mounting member forming the partition wall of the liquid chamber so as to cover the through hole. Accordingly, even when vibration of a high frequency which cannot be damped by the elastic body and a liquid is transmitted from the side of a vibration-generating portion, the elastic membrane elastically deforms and the dynamic spring constant becomes low. As a result, vibration is not easily transmitted to the side of a vibration-receiving portion.

摘要翻译： 一种防振装置，包括：第一安装构件; 具有通孔的第二安装构件; 弹性体，其被设置为可弹性变形并以插入在所述第一安装构件和所述第二安装构件之间的方式安装; 液体室，其中至少一部分隔壁由弹性体和第二安装构件形成，并且填充有液体; 以及弹性膜，其设置成可弹性变形并且固定到形成所述液体室的分隔壁的所述第二安装构件的覆盖所述通孔的部分。 因此，即使由弹性体不能被阻尼的高频振动和液体从振动产生部分的一侧传递，弹性膜弹性变形，动态弹簧常数变低。 结果，振动不容易传递到振动接收部分的一侧。

公开(公告)号：US5875762A

公开(公告)日：1999-03-02

申请号：US17690

申请日：1998-02-03

申请人： Kenichi Tsuchiya ,  Shiro Yonezawa ,  Hirofumi Ohuchi ,  Tadashi Tubakiji

发明人： Kenichi Tsuchiya ,  Shiro Yonezawa ,  Hirofumi Ohuchi ,  Tadashi Tubakiji

IPC分类号： F02D9/02 ,  F02D11/10 ,  F02D41/24 ,  F02D41/08 ,  F02M3/07

CPC分类号： F02D41/28 ,  F02D11/106

摘要： An engine controller includes various sensors for detecting a degree of throttle opening .theta. and a degree of accelerator opening .alpha. and a control unit 5 for determining the control amount .theta.c of a throttle actuator 1 from operating states, the control unit includes an A/D converter 70 for A/D converting respective degrees of opening at a predetermined resolving power, means 71 for calculating a target degree of throttle opening .theta.1 at a resolving power higher than the predetermined resolving power, means 72 for calculating a target degree of throttle opening .theta.2 at the predetermined resolving power in accordance with the target degree of throttle opening .theta.1 and means 73 for calculating a control amount in accordance with the target degree of throttle opening .theta.2, the target degree of throttle opening .theta.2 includes two points which are determined by the predetermined resolving power and control amount calculation means repeatedly controls the throttle actuator at a predetermined cycle using the target degree of throttle opening .theta.2 as the control amount under predetermined operating conditions. With this arrangement, the engine controller having a high speed and a pinpoint accuracy can be provided at a less expensive cost without using an expensive A/D converter.

摘要翻译： 发动机控制器包括用于检测节气门开度θ和加速器开度α的各种传感器，以及用于确定节气门执行器1的运行状态的控制量θc的控制单元5，控制单元包括A / D 转换器70，用于以预定分辨率转换相应的开度;装置71，用于以高于预定分辨率的分辨率计算节气门开度θ1的目标程度;装置72，用于计算目标节气门开度 根据目标节气门开度θ1的预定分辨率的θ2和用于根据目标节气门开度θ2计算控制量的装置73，目标节气门开度θ2包括两点， 由预定的分辨力确定，并且控制量计算装置重复地控制节气门致动器 或者在预定的操作条件下使用目标节气门开度θ2作为控制量。 通过这种布置，可以在不使用昂贵的A / D转换器的情况下以较便宜的成本提供具有高速度和精确定位精度的发动机控制器。

公开(公告)号：US09201654B2

公开(公告)日：2015-12-01

申请号：US13171027

申请日：2011-06-28

申请人： Jason F. Cantin ,  Jack R. Smith ,  Arnold S. Tran ,  Kenichi Tsuchiya

发明人： Jason F. Cantin ,  Jack R. Smith ,  Arnold S. Tran ,  Kenichi Tsuchiya

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/3848

摘要： Disclosed are a processor and a processing method incorporating an instruction pipeline with direction prediction (i.e., taken or not taken) for conditional branch instructions. In the embodiments, reading of a branch instruction history table (BHT) and a branch instruction target address cache (BTAC) for branch direction prediction occurs in parallel with the current instruction fetch in order to minimize delay in the next instruction fetch. Additionally, direction prediction is performed in the very next clock cycle based either on an initial direction prediction for the specific instruction, as stored in the BHT, or, if applicable, on a prior entry for the specific instruction in the BTAC. An override bit associated with each entry in the BTAC is the determining factor for whether or the BTAC or BHT is controlling. Override bits in the BTAC can be pre-established based on the branch instruction type in order to ensure prediction accuracy.

摘要翻译： 公开了一种处理器和处理方法，其结合了用于条件分支指令的具有方向预测（即采取或未采用）的指令流水线。 在实施例中，用于分支方向预测的分支指令历史表（BHT）和分支指令目标地址高速缓存（BTAC）的读取与当前指令获取并行发生，以便使下一指令提取中的延迟最小化。 另外，方向预测是在下一个时钟周期内执行的，即基于存储在BHT中的特定指令的初始方向预测，或者如果适用，在BTAC中针对特定指令的先前条目。 与BTAC中的每个条目相关联的覆盖位是否是BTAC或BHT正在控制的决定因素。 可以基于分支指令类型预先建立BTAC中的覆盖位，以确保预测精度。

公开(公告)号：US20140019737A1

公开(公告)日：2014-01-16

申请号：US13550129

申请日：2012-07-16

申请人： Andrew D. Hilton ,  Brian M. Rogers ,  Kenichi Tsuchiya

发明人： Andrew D. Hilton ,  Brian M. Rogers ,  Kenichi Tsuchiya

IPC分类号： G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/30058 ,  G06F9/3806

摘要： Branch prediction for indirect jumps, including: receiving, by a branch prediction module, a branch address for each of a plurality of executed branch instructions; receiving, by the branch prediction module, an instruction address of a current branch instruction; creating, by the branch prediction module, an execution path identifier in dependence upon the branch address for each of the plurality of executed branch instructions and the instruction address of the current branch instruction; and searching, by the branch prediction module, a branch prediction table for an entry that matches the execution path identifier.

摘要翻译： 包括：由分支预测模块接收多个执行的分支指令中的每一个的分支地址; 由分支预测模块接收当前分支指令的指令地址; 由所述分支预测模块根据所述多个执行分支指令中的每一个的分支地址和所述当前分支指令的指令地址，创建执行路径标识符; 以及由分支预测模块搜索与执行路径标识符匹配的条目的分支预测表。