公开(公告)号：US08400924B2

公开(公告)日：2013-03-19

申请号：US13238723

申请日：2011-09-21

申请人： James Wang ,  Zongjian Chen

发明人： James Wang ,  Zongjian Chen

IPC分类号： H04L12/26

CPC分类号： G06F13/385 ,  H04L47/10 ,  H04L47/39 ,  H04L49/90

摘要： In one embodiment, a receiver on a credit-based flow-controlled interface is configured to free one or more data credits early when a data payload is received that incurs fewer unused data credits within a buffer memory that is allocated at a coarser granularity than the data credits. In another embodiment, header credits and data credits are dynamically adjusted based on actual packet data payload sizes.

摘要翻译： 在一个实施例中，基于信用的流量控制接口上的接收器被配置为在接收到数据有效载荷时释放一个或多个数据信息，该数据有效载荷在缓冲存储器内产生更少的未被使用的数据信用，该缓冲存储器以比该 数据信用。 在另一个实施例中，基于实际分组数据有效载荷大小动态地调整报头信用和数据信用。

公开(公告)号：US08397049B2

公开(公告)日：2013-03-12

申请号：US12501643

申请日：2009-07-13

申请人： James Wang ,  Zongjian Chen

发明人： James Wang ,  Zongjian Chen

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F2212/6022 ,  G06F2212/6028 ,  G06F2212/654 ,  G06F2212/681 ,  G06F2212/684

摘要： In an embodiment, a memory management unit (MMU) is configured to retain a block of data that includes multiple page table entries. The MMU is configured to check the block in response to TLB misses, and to supply a translation from the block if the translation is found in the block without generating a memory read for the translation. In some embodiments, the MMU may also maintain a history of the TLB misses that have used translations from the block, and may generate a prefetch of a second block based on the history. For example, the history may be a list of the most recently used Q page table entries, and the history may show a pattern of access that are nearing an end of the block. In another embodiment, the history may comprise a count of the number of page table entries in the block that have been used.

摘要翻译： 在一个实施例中，存储器管理单元（MMU）被配置为保留包括多个页表项的数据块。 MMU被配置为响应于TLB未命中来检查块，并且如果在块中找到转换而提供来自块的转换而不产生用于转换的存储器读取。 在一些实施例中，MMU还可以维护已经使用来自块的翻译的TLB未命中的历史，并且可以基于历史生成第二块的预取。 例如，历史可以是最近使用的Q页表项的列表，并且历史可以示出接近块结束的访问模式。 在另一个实施例中，历史可以包括已经使用的块中的页表条目的数量的计数。

公开(公告)号：US07804721B2

公开(公告)日：2010-09-28

申请号：US12487035

申请日：2009-06-18

申请人： James Wang ,  Zongjian Chen

发明人： James Wang ,  Zongjian Chen

IPC分类号： G11C7/10 ,  G06F3/00 ,  G06F5/00 ,  G06F13/36

CPC分类号： G06F5/065

摘要： In one embodiment, an apparatus comprises a queue, write control logic coupled to the queue and operable in a write clock domain, and a first-in, first-out buffer (FIFO) coupled to the write control logic. The queue is configured to store a plurality of data items, wherein each data item has a type which is one of a plurality of types of data items that can be stored in the queue. The write control logic is configured to maintain write pointers that identify entries in the queue for each of the plurality of types. The write control logic is configured to update the write pointer corresponding to an input type for an input data item written to the queue. Additionally, the write control logic is configured to enqueue a write event in the FIFO to transport the enqueue event to a read clock domain different from the write clock domain.

摘要翻译： 在一个实施例中，一种装置包括队列，耦合到队列的写入控制逻辑，并且可在写入时钟域中操作，以及耦合到写入控制逻辑的先入先出缓冲器（FIFO）。 队列被配置为存储多个数据项，其中每个数据项具有可以存储在队列中的多种类型的数据项之一的类型。 写入控制逻辑被配置为维护写入指针，其针对多种类型中的每一种来标识队列中的条目。 写控制逻辑被配置为更新对应于写入队列的输入数据项的输入类型的写指针。 此外，写入控制逻辑被配置为对FIFO中的写入事件进行排队，以将入站事件传送到与写入时钟域不同的读取时钟域。

公开(公告)号：US20100165842A1

公开(公告)日：2010-07-01

申请号：US12344949

申请日：2008-12-29

申请人： James Wang ,  Zongjian Chen

发明人： James Wang ,  Zongjian Chen

IPC分类号： H04L12/24

CPC分类号： G06F13/385 ,  H04L47/10 ,  H04L47/39 ,  H04L49/90

摘要： In one embodiment, a receiver on a credit-based flow-controlled interface is configured to free one or more data credits early when a data payload is received that incurs fewer unused data credits within a buffer memory that is allocated at a coarser granularity than the data credits. In another embodiment, header credits and data credits are dynamically adjusted based on actual packet data payload sizes.

摘要翻译： 在一个实施例中，基于信用的流量控制接口上的接收器被配置为在接收到数据有效载荷时释放一个或多个数据信息，该数据有效载荷在缓冲存储器内产生更少的未被使用的数据信用，该缓冲存储器以比该 数据信用。 在另一个实施例中，基于实际分组数据有效载荷大小动态地调整报头信用和数据信用。

公开(公告)号：US11093992B2

公开(公告)日：2021-08-17

申请号：US15970188

申请日：2018-05-03

申请人： James Wang ,  Siddharth Biswal

发明人： James Wang ,  Siddharth Biswal

IPC分类号： G06Q30/00 ,  G06Q30/06 ,  G06Q50/16 ,  H04L12/58 ,  H04L29/08 ,  G06Q50/00

摘要： Systems and methods are described for efficiently meeting the needs of property buyers, sellers, and agents. Attributes of the user and of each property are combined and processed by a machine learning model. The output represents a prediction that a user will choose to view the property. Each property is ranked and displayed to the user. When the user selects a property, the interaction is used to update the machine learning model. In some cases, a natural language processing system identifies property and user attributes based on a natural language query. In some cases, a chatbot may respond to a natural language query in real time. The system may also be utilized to provide matching services for buyers or sellers to agents, or third party service providers, as well as matching buyers and sellers directly to each other, or user to other users for transaction, interaction and other needs.

公开(公告)号：US20180278215A1

公开(公告)日：2018-09-27

申请号：US15983678

申请日：2018-05-22

申请人： James Wang ,  Yuh-Min Lin ,  Kun-You Lin

发明人： James Wang ,  Yuh-Min Lin ,  Kun-You Lin

IPC分类号： H03F1/30 ,  H03F1/56 ,  H03F3/16 ,  H01L27/02

CPC分类号： H03F1/301 ,  H01L27/0255 ,  H01L27/0292 ,  H03F1/523 ,  H03F1/56 ,  H03F3/16 ,  H03F3/193 ,  H03F3/72 ,  H03F2200/18 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/387 ,  H03F2200/426 ,  H03F2200/444 ,  H03F2200/447 ,  H03F2200/451 ,  H03F2203/7231 ,  H03F2203/7236

摘要： A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

公开(公告)号：US20180269575A1

公开(公告)日：2018-09-20

申请号：US15984912

申请日：2018-05-21

申请人： James Wang

发明人： James Wang

IPC分类号： H01Q3/26 ,  G01S3/14

CPC分类号： H01Q3/2605 ,  G01S3/14

摘要： An array antenna system consists of layered construct of subarrays. Each beam pointing angle requires an antenna weight vector (AWV). A circuit tracks the changing orientation of a beam within a much larger virtual array of antenna weights. A row or column of a local RAM may be determined to be least likely to be read next and is overwritten with antenna weights more likely to be read next. An address translation circuit represents the RAM as a barrel. An adaptively adjusted antenna weight method optimizes received signal power. A beam splitting method provides a mirror beam pointing direction by wrapping around a look ahead table of antenna weight vectors when an antenna is itself gyrating or when a remote transceiver is anticipated to transit the horizon.

公开(公告)号：US20180253780A1

公开(公告)日：2018-09-06

申请号：US15970188

申请日：2018-05-03

申请人： James Wang ,  Siddharth Biswal

发明人： James Wang ,  Siddharth Biswal

IPC分类号： G06Q30/06 ,  G06Q50/16 ,  H04L12/58 ,  H04L29/08

CPC分类号： G06Q30/0631 ,  G06Q30/0627 ,  G06Q30/0641 ,  G06Q50/01 ,  G06Q50/16 ,  H04L51/02 ,  H04L51/32 ,  H04L67/22 ,  H04L67/306

摘要： Systems and methods are described for efficiently meeting the needs of property buyers, sellers, and agents. Attributes of the user and of each property are combined and processed by a machine learning model. The output represents a prediction that a user will choose to view the property. Each property is ranked and displayed to the user. When the user selects a property, the interaction is used to update the machine learning model. in some cases, a natural language processing system identifies property and user attributes based on a natural language query. In some cases, a chatbot may respond to a natural language query in real time. The system may also be utilized to provide matching services for buyers or sellers to agents, or third party service providers, as well as matching buyers and sellers directly to each other, or user to other users for transaction, interaction and other needs.

公开(公告)号：US10027028B2

公开(公告)日：2018-07-17

申请号：US15162405

申请日：2016-05-23

申请人： James Wang ,  Chak Chie

发明人： James Wang ,  Chak Chie

IPC分类号： H01Q3/00 ,  H01Q3/30 ,  H01Q1/22 ,  H01Q21/00 ,  H01Q21/06 ,  H01Q3/26 ,  H01Q3/34

摘要： A method of operation for a hierarchically elaborated phased-array antenna. Within a plurality of front end modules a phased-array processing die individually transforms phase and gain according to a register array. The register array in each RFIC is grouped into a local register group and a global register group, the local registers physically placed close in proximity to RF chains which each correspond to an element of array antenna, whereby each set of local registers control an individual antenna element and a global register controlling overall RFIC function. The method efficiently elaborates phase shift weights into a submodule of a phase array antenna system. Within each subarray phase control submodule the method recursively elaborates weights to control phase shifters. The method receives and transforms pairs of major operators and minor operators. The method distributes to each submodule determining its own base phase shift weight per its unique configuration.

公开(公告)号：US20160072186A1

公开(公告)日：2016-03-10

申请号：US14479352

申请日：2014-09-07

申请人： James Wang

发明人： James Wang

IPC分类号： H01Q3/34

CPC分类号： H01Q3/2605 ,  G01S3/14

摘要： An array antenna system consists of layered construct of subarrays. Each beam pointing angle requires an antenna weight vector (AWV). A circuit tracks the changing orientation of a beam within a much larger virtual array of antenna weights. A row or column of a local RAM may be determined to be least likely to be read next and is overwritten with antenna weights more likely to be read next. An address translation circuit represents the RAM as a barrel. An adaptively adjusted antenna weight method optimizes received signal power. A beam splitting method provides a mirror beam pointing direction by wrapping around a look ahead table of antenna weight vectors when an antenna is itself gyrating or when a remote transceiver is anticipated to transit the horizon.

摘要翻译： 阵列天线系统由分层构造的子阵列组成。 每个光束指向角需要一个天线权重向量（AWV）。 电路跟踪在更大的天线权重的虚拟阵列内的波束的变化方向。 本地RAM的行或列可以被确定为不太可能接下来读取，并且被更接近更可能读取的天线权重覆盖。 地址转换电路将RAM表示为桶。 自适应调节的天线权重法优化接收信号功率。 当天线本身旋转时或者当远程收发器预期到达地平线时，分束方法通过围绕天线加权矢量的前视表来提供镜射束指向方向。