METHOD FOR RAPID ESTIMATION OF LAYOUT-DEPENDENT THRESHOLD VOLTAGE VARIATION IN A MOSFET ARRAY
    21.
    发明申请
    METHOD FOR RAPID ESTIMATION OF LAYOUT-DEPENDENT THRESHOLD VOLTAGE VARIATION IN A MOSFET ARRAY 有权
    MOSFET阵列快速估计依赖于阈值电压变化的方法

    公开(公告)号:US20080301599A1

    公开(公告)日:2008-12-04

    申请号:US11757335

    申请日:2007-06-01

    IPC分类号: G06F17/50

    摘要: An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations.

    摘要翻译: 用于估计集成电路布局中阈值电压的布局引起的变化的自动化方法。 该方法开始于在布局内选择扩散区域以进行分析的步骤。 然后,系统识别所选区域的Si / STI边缘以及通道区域及其相关的栅极/ Si边缘。 接下来,识别每个识别的通道区域中的阈值电压变化,这需要由于纵向方向的影响而计算阈值电压变化的进一步步骤; 计算由于横向影响引起的阈值电压变化; 并且将纵向和横向变化组合以提供整体变化。 最后,通过组合来自各个通道变化的变化来确定总体变化。

    Methods for forming a transistor
    23.
    发明授权
    Methods for forming a transistor 有权
    形成晶体管的方法

    公开(公告)号:US07413957B2

    公开(公告)日:2008-08-19

    申请号:US11123588

    申请日:2005-05-06

    IPC分类号: H01L21/336

    摘要: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.

    摘要翻译: 提供了用于在诸如金属氧化物晶体管的衬底上形成半导体器件中沉积材料的方法。 在一个实施例中,本发明通常提供一种处理衬底的方法,包括在具有第一导电性的衬底上形成栅极电介质,在栅极电介质上形成栅电极,在栅极的横向相对的侧壁上形成第一对侧壁间隔物 在电极的相对侧蚀刻一对源极/漏极区域定义,在源/漏区定义中选择性地沉积硅 - 锗材料,以及在沉积的硅 - 锗材料中注入掺杂剂以形成源极/漏极 区域具有第二导电性。

    Method of IC production using corrugated substrate
    24.
    发明授权
    Method of IC production using corrugated substrate 有权
    使用波纹基板的IC生产方法

    公开(公告)号:US07265008B2

    公开(公告)日:2007-09-04

    申请号:US11173230

    申请日:2005-07-01

    IPC分类号: H01L21/336 H01L21/8234

    摘要: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

    摘要翻译: 通过在具有预先存在的半导体材料的脊(即,“波纹状基板”)的基板上形成MOSFET,可以克服与常规半导体制造工艺相关的分辨率限制,并且可以可靠地实现高性能的低功率晶体管, 重复生产。 在实际的器件形成之前形成波纹状衬底可以使用通常不适于器件生产的高精度技术来产生波纹衬底上的脊。 随后将高精度脊结合到其沟道区中的MOSFET通常将显示出比使用不能提供相同程度的图案精度的基于光刻技术形成的类似的MOSFET更精确和更少可变的性能。 附加的性能增强技术,例如脉冲形掺杂和“包裹”栅极可以与分段通道区域一起使用,以进一步提高器件性能。

    Segmented channel MOS transistor
    25.
    发明授权
    Segmented channel MOS transistor 有权
    分段通道MOS晶体管

    公开(公告)号:US07247887B2

    公开(公告)日:2007-07-24

    申请号:US11173237

    申请日:2005-07-01

    IPC分类号: H01L29/43

    摘要: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

    摘要翻译: 通过在具有预先存在的半导体材料的脊(即,“波纹状基板”)的基板上形成MOSFET,可以克服与常规半导体制造工艺相关的分辨率限制,并且可以可靠地实现高性能的低功率晶体管, 重复生产。 在实际的器件形成之前形成波纹状衬底可以使用通常不适于器件生产的高精度技术来产生波纹衬底上的脊。 随后将高精度脊结合到其沟道区中的MOSFET通常将显示出比使用不能提供相同程度的图案精度的基于光刻技术形成的类似的MOSFET更精确和更少可变的性能。 附加的性能增强技术,例如脉冲形掺杂和“包裹”栅极可以与分段通道区域一起使用,以进一步提高器件性能。

    Self-aligned via interconnect using relaxed patterning exposure
    26.
    发明授权
    Self-aligned via interconnect using relaxed patterning exposure 有权
    通过使用松弛图案曝光的互连自对准

    公开(公告)号:US08813012B2

    公开(公告)日:2014-08-19

    申请号:US13550460

    申请日:2012-07-16

    IPC分类号: G06F17/50

    摘要: Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.

    摘要翻译: 通过使用松弛图案曝光的互连自对准。 根据第一方法实施例,一种用于控制用于设计集成电路的物理特征的计算机辅助设计(CAD)系统的方法包括:访问用于第一金属层上的第一金属迹线的第一图案,访问用于第二金属层的第二图案 垂直于第一金属层的第二金属层上的金属迹线,并且访问第一和第二金属迹线之间的预期互连的精确图案。 操作预定互连的精确模式以形成指示允许通孔的多个通用区域的不精确的通孔图案。 通过图案的不精确性用于集成电路制造过程中,与形成第一和第二金属层的操作一起形成用于互连预期互连的多个自对准通孔。

    Analysis of stress impact on transistor performance
    27.
    发明授权
    Analysis of stress impact on transistor performance 有权
    应力对晶体管性能的影响分析

    公开(公告)号:US08762924B2

    公开(公告)日:2014-06-24

    申请号:US12510188

    申请日:2009-07-27

    IPC分类号: G06F17/50

    摘要: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

    摘要翻译: 粗略地描述了一种用于近似集成电路布局中的沟道区域中的应力诱导迁移率增强的方法,包括近似在通道中的多个采样点中的每一个处的应力,将每个采样点处的应力近似转换为 相应的移动性增强值,并在所有采样点平均移动性增强值。 该方法实现了集成电路应力分析,其考虑了由多个应力产生机制所产生的应力,具有沿通道长度以外的矢量分量的应力,以及由于在邻域中存在其它结构的应力贡献(包括缓解) 正在研究的频道区域,除了最接近的STI接口。 该方法还能够对大型布局区域甚至全芯片布局进行应力分析,而不会导致完整TCAD仿真的计算成本。

    Analysis of stress impact on transistor performance

    公开(公告)号:US08713510B2

    公开(公告)日:2014-04-29

    申请号:US12510185

    申请日:2009-07-27

    IPC分类号: G06F17/50

    摘要: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

    Analysis of stress impact on transistor performance

    公开(公告)号:US08407634B1

    公开(公告)日:2013-03-26

    申请号:US11291294

    申请日:2005-12-01

    IPC分类号: G06F9/45

    摘要: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

    THRESHOLD ADJUSTMENT OF TRANSISTORS BY CONTROLLED S/D UNDERLAP
    30.
    发明申请
    THRESHOLD ADJUSTMENT OF TRANSISTORS BY CONTROLLED S/D UNDERLAP 审中-公开
    通过控制的S / D底线调整晶体管的阈值

    公开(公告)号:US20130026575A1

    公开(公告)日:2013-01-31

    申请号:US13193320

    申请日:2011-07-28

    IPC分类号: H01L27/12 H01L21/336

    摘要: Roughly described, an integrated circuit device has formed on a substrate a plurality of transistors including a first subset of at least one transistor and a second subset of at least one transistor, wherein all of the transistors in the first subset have one underlap distance and all of the transistors in the second subset have a different underlap distance. The transistors in the first and second subsets preferably have different threshold voltages, and preferably realize different points on the high performance/low power tradeoff.

    摘要翻译: 粗略地描述,集成电路器件已经在衬底上形成多个晶体管,其包括至少一个晶体管的第一子集和至少一个晶体管的第二子集,其中第一子集中的所有晶体管具有一个下层距离,并且全部 的第二子集中的晶体管具有不同的底层距离。 第一和第二子集中的晶体管优选地具有不同的阈值电压,并且优选地在高性能/低功率权衡上实现不同的点。