公开(公告)号：US20060017118A1

公开(公告)日：2006-01-26

申请号：US11184855

申请日：2005-07-20

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/6656 ,  H01L27/10885 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a semiconductor device having a spacer pattern and methods of forming the same that includes a lower interconnection pattern on a semiconductor substrate. A lower interconnection spacer covers sidewalls of the lower interconnection pattern. Spacer patterns cover the lower interconnection spacer of the lower interconnection pattern and disposed on the semiconductor substrate. An upper interconnection pattern is formed between the spacer patterns.

摘要翻译： 本发明提供一种具有间隔图案的半导体器件及其形成方法，其包括在半导体衬底上的下部互连图案。 下互连间隔件覆盖下互连图案的侧壁。 间隔图案覆盖下部互连图案的下部互连间隔件并且设置在半导体衬底上。 在间隔物图案之间形成上部互连图案。

公开(公告)号：US20050142756A1

公开(公告)日：2005-06-30

申请号：US11020827

申请日：2004-12-22

申请人： Je-Min Park ,  Dong-Won Shin ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Dong-Won Shin ,  Yoo-Sang Hwang

IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L21/4763 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/76895 ,  H01L27/0629 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

摘要： A method of fabricating a semiconductor memory device and a structure that forms both a resistor and an etching protection layer to reduce a contact resistance. The method of fabricating a semiconductor memory device according to the invention includes forming an insulation layer on a semiconductor substrate having a cell array region, a core region, and a peripheral region, each having at least one transistor formed therein, and forming both a first landing pad in the core region on the insulation layer and a second landing pad in the peripheral region, the first landing pad being overlapped with a part of a first conductive line. The invention reduces the contact resistance and prevents or minimizes a device failure caused by a misalignment, with the simplified process.

摘要翻译： 制造半导体存储器件的方法和形成电阻器和蚀刻保护层的结构以降低接触电阻。 根据本发明的制造半导体存储器件的方法包括在具有单元阵列区域，芯区域和周边区域的半导体衬底上形成绝缘层，每个晶体管阵列区域和外围区域具有形成在其中的至少一个晶体管，并且形成第一 在绝缘层上的芯区域中的着陆焊盘和外围区域中的第二着陆焊盘，第一着陆焊盘与第一导电线的一部分重叠。 本发明通过简化的过程降低了接触电阻并且防止或最小化由不对准引起的设备故障。

公开(公告)号：US20050095779A1

公开(公告)日：2005-05-05

申请号：US10961896

申请日：2004-10-08

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/20 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L28/20 ,  H01L21/76838 ,  H01L27/0629

摘要： Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.

摘要翻译： 形成集成电路器件的方法可以包括在集成电路衬底上形成绝缘层，在绝缘层上形成第一导电层，在第一导电层上形成第二导电层，使第一导电层位于第二导电层之间 导电层和绝缘层。 此外，第一导电层可以是第一材料的层，第二导电层可以是第二材料的层，并且第一和第二材料可以不同。 可以在第二导电层中形成孔，使得第一导电层的一部分通过该孔露出。 在第二导电层中形成孔之后，可以对第一和第二导电层进行图案化，以使第一导电层和第二导电层的围绕通过孔露出的部分的部分被去除，同时保持第一导电层的部分 以前暴露在洞里。

公开(公告)号：US09601420B2

公开(公告)日：2017-03-21

申请号：US14018709

申请日：2013-09-05

申请人： Yoo-Sang Hwang ,  Hyun-Woo Chung ,  Dae-Ik Kim

发明人： Yoo-Sang Hwang ,  Hyun-Woo Chung ,  Dae-Ik Kim

IPC分类号： H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L27/108 ,  H01L23/532 ,  H01L21/762

CPC分类号： H01L23/49811 ,  H01L21/76229 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality of contact plugs arranged in a row along the first direction and having sidewall surfaces facing the conductive line with air spaces between the sidewall surfaces and the conductive line, and a support interposed between the insulating capping line and the contact plugs to limit the height of the air spaces. The width of the support varies or the support is present only intermittently in the first direction. In a method of manufacturing the semiconductor devices, a sacrificial spacer is formed on the side of the stack structure, the spacer is recessed, a support layer is formed in the recess, the support layer is etched to form the support, and then the remainder of the spacer is removed to provide the air spaces.

公开(公告)号：US20130288472A1

公开(公告)日：2013-10-31

申请号：US13761376

申请日：2013-02-07

申请人： Jay-Bok Choi ,  Yoo-Sang Hwang ,  Ah-Young Kim ,  Ye-Ro Lee ,  Gyo-Young Jin ,  Hyeong-sun Hong

发明人： Jay-Bok Choi ,  Yoo-Sang Hwang ,  Ah-Young Kim ,  Ye-Ro Lee ,  Gyo-Young Jin ,  Hyeong-sun Hong

IPC分类号： H01L29/423

CPC分类号： H01L29/42312 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/4236 ,  H01L29/66621

摘要： A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.

摘要翻译： 制造半导体器件的方法包括在衬底中形成第一和第二平行场区域，所述平行场区域沿第一方向延伸，在形成的第一和第二栅极沟槽中形成第一和第二栅极覆盖层 在基板中分别去除栅极覆盖层，使得第一着陆焊盘孔被扩展以部分地覆盖掩埋在衬底中的栅极覆盖层，在第一空间中形成层叠焊盘材料层，并形成位线接触层 通过将着陆垫材料层平坦化到覆盖层的顶表面的水平面。

公开(公告)号：US20090087962A1

公开(公告)日：2009-04-02

申请号：US12325694

申请日：2008-12-01

申请人： Min-Hee Cho ,  Yoo-Sang Hwang ,  Byung-Hyun Lee

发明人： Min-Hee Cho ,  Yoo-Sang Hwang ,  Byung-Hyun Lee

IPC分类号： H01L21/02

CPC分类号： H01L27/10894 ,  H01L23/544 ,  H01L27/10814 ,  H01L28/91 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region.

摘要翻译： 在制造具有对准键和由此制造的半导体器件的半导体器件的方法中。 制造半导体器件的方法包括提供具有划线通道区域和单元区域的半导体衬底。 蚀刻阻挡图案和栅极图案分别形成在划线路区域和单元区域上。 形成第一层间绝缘层以覆盖蚀刻阻挡图案和栅极图案。 分别在划线路区域和单元区域的第一层间绝缘层上形成初步对准键图案和位线图案。 形成第二层间绝缘层以覆盖初步对准键图案和位线图案。 将第二层间绝缘层和第一层间绝缘层图案化以暴露蚀刻阻挡图案，从而在划线路区域中形成对准键图案，同时在单元区域中形成存储节点接触开口。

公开(公告)号：US06720269B2

公开(公告)日：2004-04-13

申请号：US10347219

申请日：2003-01-21

申请人： Byung-Jun Park ,  Yoo-Sang Hwang

发明人： Byung-Jun Park ,  Yoo-Sang Hwang

IPC分类号： H01L21311

CPC分类号： H01L27/10855 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10885

摘要： A self-aligned contact structure in a semiconductor device and methods for making such contact structure wherein the semiconductor device has a semiconductor substrate having active regions, an interlayer insulating layer covering the semiconductor substrate excluding at least a portion of each active region, at least two parallel interconnections on the interlayer insulating layer, at least one active region being relatively disposed between the at least two parallel interconnections, each interconnection having sidewalls, bottom and a width (x), a mask pattern having a top portion (z) and a bottom portion (y) formed on each interconnection, and a conductive layer pattern penetrating at least a portion of the interlayer insulating layer between the mask pattern and being electrically connected to at least one active region, wherein: x≦y≦z and x

摘要翻译： 半导体器件中的自对准接触结构以及用于制造这种接触结构的方法，其中半导体器件具有具有有源区的半导体衬底，覆盖半导体衬底的层间绝缘层，不包括每个有源区的至少一部分，至少两个 所述层间绝缘层上的平行互连，至少一个有源区相对设置在所述至少两个平行互连之间，每个互连具有侧壁，底部和宽度（x），具有顶部（z）和底部 形成在每个互连上的部分（y），以及穿透掩模图案之间的层间绝缘层的至少一部分并且与至少一个有源区电连接的导电层图案，其中：x <= y <= z和x

公开(公告)号：US06534813B1

公开(公告)日：2003-03-18

申请号：US09889588

申请日：2001-08-02

申请人： Byung-Jun Park ,  Yoo-Sang Hwang

发明人： Byung-Jun Park ,  Yoo-Sang Hwang

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10885

摘要： A self-aligned contact structure in a semiconductor device and methods of forming the same are provided, wherein the self-aligned contact structure in the semiconductor device comprises a semiconductor substrate having active regions; an interlayer insulating layer covering the semiconductor substrate excluding at least a portion of each active region; at least two parallel interconnections on the interlayer insulating layer, at least one active region being relatively disposed between the at least two parallel interconnections, each interconnection having sidewalls, a bottom and a width (x); a mask pattern having a top portion of width (z) and a bottom portion of width (y) formed on each interconnection; and a conductive layer pattern penetrating at least a portion of the interlayer insulating layer between the mask pattern and being electrically connected to at least one active region, wherein x≦y≦z and x

摘要翻译： 提供半导体器件中的自对准接触结构及其形成方法，其中半导体器件中的自对准接触结构包括具有有源区的半导体衬底; 覆盖半导体衬底的层间绝缘层，所述层间绝缘层不包括每个有源区的至少一部分; 在所述层间绝缘层上的至少两个平行互连，至少一个有源区相对设置在所述至少两个平行互连之间，每个互连具有侧壁，底部和宽度（x）; 具有形成在每个互连上的宽度（z）的顶部和宽度（y）的底部的掩模图案; 以及导电层图案，其穿透所述掩模图案之间的所述层间绝缘层的至少一部分并与至少一个有源区电连接，其中x <= y

公开(公告)号：US07888724B2

公开(公告)日：2011-02-15

申请号：US11316166

申请日：2005-12-22

申请人： Jong-Seo Hong ,  Jeong-Sic Jeon ,  Chun-Suk Suh ,  Yoo-Sang Hwang

发明人： Jong-Seo Hong ,  Jeong-Sic Jeon ,  Chun-Suk Suh ,  Yoo-Sang Hwang

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852

摘要： A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.

摘要翻译： 公开了一种半导体存储器件的电容器及其形成方法。 衬垫层间绝缘层设置在有源区的半导体衬底上。 着陆垫和中央着陆垫分别设置在活动区域​​的周边部分和中心部分中，以穿透垫层间绝缘层。 中央着陆垫的上表面与着陆垫的上表面具有不同的面积。 掩埋层间绝缘层形成在焊盘层间绝缘层上，以覆盖着陆焊盘和中央着陆焊盘。 在相应的着陆焊盘上形成埋入的插塞以穿透埋入的层间绝缘层。 下电极形成在埋地塞上。

公开(公告)号：US07473619B2

公开(公告)日：2009-01-06

申请号：US11232666

申请日：2005-09-22

申请人： Min-Hee Cho ,  Yoo-Sang Hwang ,  Byung Hyun Lee

发明人： Min-Hee Cho ,  Yoo-Sang Hwang ,  Byung Hyun Lee

IPC分类号： H01L21/46

CPC分类号： H01L27/10894 ,  H01L23/544 ,  H01L27/10814 ,  H01L28/91 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region.