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    METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING ALIGNMENT KEY AND SEMICONDUCTOR DEVICE FABRICATED THEREBY
    1.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING ALIGNMENT KEY AND SEMICONDUCTOR DEVICE FABRICATED THEREBY 有权
    具有对准键的半导体器件的制造方法及其制造的半导体器件

    公开(公告)号：US20090087962A1

    公开(公告)日：2009-04-02

    申请号：US12325694

    申请日：2008-12-01

    申请人： Min-Hee Cho ,  Yoo-Sang Hwang ,  Byung-Hyun Lee

    发明人： Min-Hee Cho ,  Yoo-Sang Hwang ,  Byung-Hyun Lee

    IPC分类号： H01L21/02

    CPC分类号： H01L27/10894 ,  H01L23/544 ,  H01L27/10814 ,  H01L28/91 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region.

    摘要翻译： 在制造具有对准键和由此制造的半导体器件的半导体器件的方法中。 制造半导体器件的方法包括提供具有划线通道区域和单元区域的半导体衬底。 蚀刻阻挡图案和栅极图案分别形成在划线路区域和单元区域上。 形成第一层间绝缘层以覆盖蚀刻阻挡图案和栅极图案。 分别在划线路区域和单元区域的第一层间绝缘层上形成初步对准键图案和位线图案。 形成第二层间绝缘层以覆盖初步对准键图案和位线图案。 将第二层间绝缘层和第一层间绝缘层图案化以暴露蚀刻阻挡图案，从而在划线路区域中形成对准键图案，同时在单元区域中形成存储节点接触开口。

    Method of fabricating semiconductor device having alignment key and semiconductor device fabricated thereby
    3.
    发明授权
    Method of fabricating semiconductor device having alignment key and semiconductor device fabricated thereby 有权
    制造具有对准键的半导体器件和由此制造的半导体器件的方法

    公开(公告)号：US07595251B2

    公开(公告)日：2009-09-29

    申请号：US12325694

    申请日：2008-12-01

    申请人： Min-Hee Cho ,  Yoo-Sang Hwang ,  Byung-Hyun Lee

    发明人： Min-Hee Cho ,  Yoo-Sang Hwang ,  Byung-Hyun Lee

    IPC分类号： H01L21/76

    CPC分类号： H01L27/10894 ,  H01L23/544 ,  H01L27/10814 ,  H01L28/91 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region.

    摘要翻译： 在制造具有对准键和由此制造的半导体器件的半导体器件的方法中。 制造半导体器件的方法包括提供具有划线通道区域和单元区域的半导体衬底。 蚀刻阻挡图案和栅极图案分别形成在划线路区域和单元区域上。 形成第一层间绝缘层以覆盖蚀刻阻挡图案和栅极图案。 分别在划线路区域和单元区域的第一层间绝缘层上形成初步对准键图案和位线图案。 形成第二层间绝缘层以覆盖初步对准键图案和位线图案。 将第二层间绝缘层和第一层间绝缘层图案化以暴露蚀刻阻挡图案，从而在划线路区域中形成对准键图案，同时在单元区域中形成存储节点接触开口。

    Methods for forming resistors including multiple layers for integrated circuit devices
    7.
    发明授权
    Methods for forming resistors including multiple layers for integrated circuit devices 有权
    用于形成用于集成电路器件的多层电阻器的方法

    公开(公告)号：US07855120B2

    公开(公告)日：2010-12-21

    申请号：US11780026

    申请日：2007-07-19

    申请人： Je-Min Park ,  Yoo-Sang Hwang

    发明人： Je-Min Park ,  Yoo-Sang Hwang

    IPC分类号： H01L21/20

    CPC分类号： H01L28/20 ,  H01L21/76838 ,  H01L27/0629

    摘要： Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.

    摘要翻译： 形成集成电路器件的方法可以包括在集成电路衬底上形成绝缘层，在绝缘层上形成第一导电层，在第一导电层上形成第二导电层，使第一导电层位于第二导电层之间 导电层和绝缘层。 此外，第一导电层可以是第一材料的层，第二导电层可以是第二材料的层，并且第一和第二材料可以不同。 可以在第二导电层中形成孔，使得第一导电层的一部分通过该孔露出。 在第二导电层中形成孔之后，可以对第一和第二导电层进行图案化，以使第一导电层和第二导电层的围绕通过孔露出的部分的部分被去除，同时保持第一导电层的部分 以前暴露在洞里。

    Method of fabricating semiconductor devices having buried contact plugs
    8.
    发明授权
    Method of fabricating semiconductor devices having buried contact plugs 有权
    制造具有埋入式接触塞的半导体器件的方法

    公开(公告)号：US07749834B2

    公开(公告)日：2010-07-06

    申请号：US11364635

    申请日：2006-02-27

    申请人： Je-Min Park ,  Yoo-Sang Hwang ,  Seok-Soon Song

    发明人： Je-Min Park ,  Yoo-Sang Hwang ,  Seok-Soon Song

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10855 ,  H01L27/10817

    摘要： A method includes forming a lower dielectric layer on a semiconductor substrate, forming a bit line landing pad and a storage landing pad that penetrate the lower dielectric layer, covering the lower dielectric layer, the bit line landing pad, and the storage landing pad with an intermediate dielectric layer, forming an upper dielectric layer on the intermediate dielectric layer, partially removing the upper dielectric layer and the intermediate dielectric layer to form a contact opening that exposes the storage landing pad and a portion of the lower dielectric layer, forming a contact spacer on an inner wall of the contact opening, and filling the contact opening with a contact plug, a top surface of the contact plug larger than a surface of the contact plug that is in contact with the storage landing pad, the top surface of the contact plug eccentric in relation to the storage landing pad.

    摘要翻译： 一种方法包括在半导体衬底上形成下电介质层，形成位线着陆焊盘和穿透下电介质层的存储着陆焊盘，覆盖下电介质层，位线着陆焊盘和存储着陆焊盘 中间介电层，在中间介电层上形成上电介质层，部分地去除上电介质层和中间电介质层，以形成暴露存储着陆焊盘和下电介质层的一部分的接触开口，形成接触间隔物 在接触开口的内壁上，并用接触塞填充接触开口，接触插塞的顶表面大于接触插塞的与储存着陆垫接触的表面，触头顶表面 相对于存储着陆垫插头偏心。

    Semiconductor devices having DRAM cells and methods of fabricating the same
    9.
    发明授权
    Semiconductor devices having DRAM cells and methods of fabricating the same 有权
    具有DRAM单元的半导体器件及其制造方法

    公开(公告)号：US07247906B2

    公开(公告)日：2007-07-24

    申请号：US11252963

    申请日：2005-10-17

    申请人： Je-Min Park ,  Yoo-Sang Hwang

    发明人： Je-Min Park ,  Yoo-Sang Hwang

    IPC分类号： H01L29/76 ,  H01L21/8242

    CPC分类号： H01L28/91 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855

    摘要： A semiconductor device comprises bit line landing pads and storage landing pads disposed on both sides of the bit line landing pads overlying a substrate. A bit line interlayer insulating layer overlies the bit line and storage landing pads. A plurality of bit line patterns are disposed on the bit line interlayer insulating layer. The bit line patterns each include a bit line and a bit line capping layer pattern. Line insulating layer patterns are placed on a top surface of the bit line interlayer insulating layer. Upper contact holes are placed in a region between the bit line patterns and higher than upper surfaces of the bit lines. Contact hole spacers cover the side walls of the upper contact holes. Lower contact holes are self-aligned with the upper contact holes and extend through the line insulating layer patterns and the bit line interlayer insulating layer, thereby exposing the storage node landing pads.

    摘要翻译： 半导体器件包括位线着陆焊盘和设置在覆盖衬底的位线着色焊盘的两侧上的存储着陆焊盘。 位线层间绝缘层覆盖位线和存储着陆焊盘。 多个位线图案设置在位线层间绝缘层上。 位线图案各自包括位线和位线覆盖层图案。 线绝缘层图案被放置在位线层间绝缘层的顶表面上。 上接触孔位于位线图案之间的区域中，高于位线的上表面。 接触孔间隔件覆盖上接触孔的侧壁。 下接触孔与上接触孔自对准并延伸穿过线绝缘层图案和位线层间绝缘层，从而暴露存储节点着陆焊盘。

    Semiconductor memory device and method of manufacturing the same
    10.
    发明授权
    Semiconductor memory device and method of manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US07145195B2

    公开(公告)日：2006-12-05

    申请号：US10803592

    申请日：2004-03-17

    申请人： Je-Min Park ,  Yoo-Sang Hwang

    发明人： Je-Min Park ,  Yoo-Sang Hwang

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10855 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/91

    摘要： A semiconductor device comprises a semiconductor substrate including an isolation region defining an active area with a plurality of source/drain regions. A contact pad layer is formed on the semiconductor substrate and includes gate line structures, first contact pads connected to parts of the source/drain regions, second contact pads connected to the other source/drain regions. A first interlevel dielectric layer covers the gate line structures and the first and second contact pads. A bit line contact plug layer is formed on the contact pad layer and includes lower storage node contact plugs connected to the first contact pads, bit line contact plugs connected to the second contact pads. A protective layer pattern is formed on the second contact pads to prevent the second contact pads from being connected to the lower storage node contact plugs and/or upper storage node contact plugs.

    摘要翻译： 半导体器件包括半导体衬底，其包括限定具有多个源极/漏极区域的有源区域的隔离区域。 接触焊盘层形成在半导体衬底上并且包括栅极线结构，连接到源极/漏极区的一部分的第一接触焊盘，连接到另一个源极/漏极区的第二接触焊盘。 第一层间电介质层覆盖栅极线结构以及第一和第二接触焊盘。 位线接触插塞层形成在接触焊盘层上，并且包括连接到第一接触焊盘的下部存储节点接触插塞，连接到第二接触焊盘的位线接触插头。 在第二接触焊盘上形成保护层图案，以防止第二接触焊盘与下部存储节点接触插塞和/或上部存储节点接触插头连接。