公开(公告)号：US5579265A

公开(公告)日：1996-11-26

申请号：US393464

申请日：1995-02-27

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  G11C7/00

CPC classification number: G11C29/84 ,  G11C29/24

Abstract: The disclosure pertains to a memory redundancy circuit. A main memory may, if there should be defective zones (defective columns for example), be replaced by a redundancy memory. A defective address memory is initialized during the testing of the main memory. During normal operation relating to access to the main memory, each main memory address is compared with all the defective addresses to replace the zone of the main memory with a redundancy memory. During the testing of the main memory, it is generally necessary to initialize each address of the defective address memory. This causes time to be lost if the main memory is fault-free. The disclosure provides for an inhibition circuit that can be used to put the defective address memory out of service or to make its operation ineffective, and to do so permanently. Application to integrated circuit memories.

Abstract translation: 本公开涉及存储器冗余电路。 如果存在缺陷区（例如有缺陷的列），主存储器可以由冗余存储器替代。 在主存储器的测试期间初始化缺陷地址存储器。 在与访问主存储器相关的正常操作期间，将每个主存储器地址与所有缺陷地址进行比较以用冗余存储器替换主存储器的区域。 在主存储器的测试期间，通常需要初始化缺陷地址存储器的每个地址。 如果主存储器无故障，则会导致时间丢失。 本公开提供了可用于将缺陷地址存储器停止服务或使其操作无效并且永久地执行的抑制电路。 应用于集成电路存储器。

公开(公告)号：US5561621A

公开(公告)日：1996-10-01

申请号：US381529

申请日：1995-01-31

Applicant: Jean Devin ,  Jean-Michel Mirabel

Inventor： Jean Devin ,  Jean-Michel Mirabel

IPC: G11C17/00 ,  G11C15/04 ,  G11C16/04 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

CPC classification number: G11C16/0441 ,  G11C15/046 ,  G11C29/78

Abstract: The disclosure relates to integrated circuits and, notably, to memories. A description is given of a bistable type of programmable, non-volatile memory, namely a memory that can take one state or another by the programming of one of two floating-gate transistors of the cell. To program a cell such as this, there are two transistors for the application of a programming voltage (VPRG). In order that the signals going through the programming paths (in particular the address signals) may not disturb the state of the cell in reading mode, provision is made for two isolation transistors interposed between the transistors for the application of the programming voltage and the drains of the floating-gate transistors. These isolation transistors are made conductive by a signal CAMSEL solely for a programming operation and solely for only one group of cells to be programmed. These cells can be applied notably to the storage of defective address elements in the redundancy circuits of large-capacity memories.

Abstract translation: 本公开涉及集成电路，特别是涉及存储器。 给出了双稳态类型的可编程非易失性存储器的描述，即通过对单元的两个浮栅晶体管之一编程可以采取一种状态的存储器。 为了对这样的单元进行编程，有两个用于编程电压（VPRG）的晶体管。 为了使通过编程路径（特别是地址信号）的信号可能不会在读取模式下干扰单元的状态，因此为了应用编程电压和漏极，提供插在晶体管之间的两个隔离晶体管 的浮栅晶体管。 这些隔离晶体管仅由用于编程操作的信号CAMSEL导通，并且仅用于仅一组要编程的单元。 这些单元可以特别地应用于大容量存储器的冗余电路中的有缺陷地址元件的存储。

公开(公告)号：US4947375A

公开(公告)日：1990-08-07

申请号：US163270

申请日：1988-03-02

Applicant: Jean Marie Gaultier ,  Jean Devin

Inventor： Jean Marie Gaultier ,  Jean Devin

IPC: G11C11/413 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/785 ,  G11C29/808

Abstract: A method for the addressing of redundant elements of an integrated circuit memory is disclosed. This memory comprises an array of row memory elements and column memory elements, respectively addressable by row addresses and column addresses, at least one battery of fuses to store the address of a faulty element of the memory. The method consists:for one battery, in associating said battery with a row/column address pair;in memorizing, through the blowing of certain fuses in the battery after the testing of a memory element, the address either of a column element if the faulty element is a column element or that of a row element if the faulty element is a row element;and in enabling only the row addresses when the stored address is that of a row element or only the column addresses when the stored address is that of a column element, to address either a row redundant element or a column redundant element.

Abstract translation: 公开了一种用于寻址集成电路存储器的冗余元件的方法。 该存储器包括可分别由行地址和列地址寻址的行存储器元件和列存储器元件的阵列，至少一个熔丝电池，用于存储存储器的故障元件的地址。 该方法包括：对于一个电池，将所述电池与行/列地址对相关联; 通过在测试存储器元件之后吹过电池中的某些保险丝来记住，如果故障元件是列元素，则列元素的地址或者如果有缺陷的元素是行元素则是行元素的地址; 并且当存储的地址是行元素的地址时，仅启用行地址，或者当存储的地址是列元素的地址时，仅列出地址，以寻址行冗余元素或列冗余元素。

公开(公告)号：US07330381B2

公开(公告)日：2008-02-12

申请号：US11008586

申请日：2004-12-09

Applicant: Sebastien Zink ,  Paola Cavaleri ,  Bruno Leconte ,  Jean Devin ,  Francois Maugain

Inventor： Sebastien Zink ,  Paola Cavaleri ,  Bruno Leconte ,  Jean Devin ,  Francois Maugain

IPC: G06F12/06

CPC classification number: G11C8/12 ,  G11C8/04

Abstract: The present invention relates to a memory on a silicon microchip, comprising a serial input/output and an integrated memory array addressable under N bits. According to the present invention, the memory comprises means for storing a most significant address allocated to the memory within an extended memory array addressable with an extended address of N+K bits, an extended address counter for storing an extended address received at the serial input/output of the memory, the extended address comprising N least significant bits that are applied to the integrated memory array, and K most significant bits, means for comparing the K most significant bits with the most significant address allocated to the memory, and means for preventing the execution of a command for reading or writing the integrated memory array if the K most significant address bits are different to the most significant address allocated to the memory. In one embodiment, a ready/busy pad is provided that is taken to a selected potential to prevent access to the memory.

Abstract translation: 本发明涉及硅微芯片上的存储器，包括串行输入/输出和可在N位下寻址的集成存储器阵列。 根据本发明，存储器包括用于存储可扩展存储器阵列中分配给存储器的最高有效地址的装置，可扩展地址为N + K位，扩展地址计数器用于存储在串行输入端处接收的扩展地址 存储器的输出，包括施加到集成存储器阵列的N个最低有效位的扩展地址和K个最高有效位，用于将K个最高有效位与分配给存储器的最高有效位进行比较的装置，以及用于 如果K个最高有效地址位与分配给存储器的最高有效地址不同，则阻止执行用于读取或写入集成存储器阵列的命令。 在一个实施例中，提供了一个就绪/忙碌垫，其被采取到选择的潜力以防止对存储器的访问。

公开(公告)号：US06933764B2

公开(公告)日：2005-08-23

申请号：US10721058

申请日：2003-11-24

Applicant: Jean Devin

Inventor： Jean Devin

IPC: H02H9/04 ,  H03K5/08

CPC classification number: H02H9/046

Abstract: An integrated circuit having a voltage generator supplying a determined voltage, a voltage-limiting circuit arranged at the output of the voltage generator, the voltage-limiting circuit having at least one PN junction formed by a diode-arranged MOS transistor, the PN junction having a breakdown voltage defining a threshold for triggering the voltage-limiting circuit as from which the PN junction is on by avalanche effect, at least one load in series with the PN junction for limiting an avalanche current passing through the PN junction when the PN junction is on, and at least one switch in parallel with the PN junction and the load, the switch arranged in the open state when the PN junction is off and to be in the closed state when the PN junction is on.

Abstract translation: 一种具有提供确定电压的电压发生器的集成电路，布置在电压发生器的输出端的限压电路，该限压电路具有由二极管配置的MOS晶体管形成的至少一个PN结，该PN结具有 限定阈值的击穿电压，用于触发由PN结接通的雪崩效应的电压限制电路，与PN结串联的至少一个负载，用于限制当PN结处于PN结处时通过PN结的雪崩电流 以及与PN结和负载并联的至少一个开关，当PN结关闭时，开关布置成处于断开状态，并且当PN结接通时处于闭合状态。

公开(公告)号：US20050078503A1

公开(公告)日：2005-04-14

申请号：US10921365

申请日：2004-08-18

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C8/20 ,  G11C11/22 ,  G11C16/22

CPC classification number: G11C16/22

Abstract: A memory circuit comprising a memory area for storing data, a non-volatile memory area for storing at least one identification code, and a pin for storing the identification code in the non-volatile memory area. The memory circuit further comprising a programmable register in which a programmable state is fixed, wherein the programmable state indicates if the identification code has been stored in the non-volatile memory area, and a logic module which blocks any subsequent changes to the identification code fixed in the non-volatile memory area in response to the programmable state in the programmable register indicating that the identification code has been stored in the non-volatile area. The invention also relates to an associated method. The invention is useful particularly to avoid fraudulent reprogramming of the area containing the identification code. The invention also relates to an associated method.

Abstract translation: 一种存储电路，包括用于存储数据的存储区域，用于存储至少一个识别码的非易失性存储区域和用于将所述识别码存储在所述非易失性存储区域中的引脚。 存储器电路还包括其中可编程状态是固定的可编程寄存器，其中可编程状态指示识别码是否已被存储在非易失性存储器区域中，以及逻辑模块，其阻止对固定的识别码的任何后续改变 响应于所述可编程寄存器中的所述可编程状态指示所述识别码已被存储在所述非易失性区域中，在所述非易失性存储器区域中。 本发明还涉及一种相关联的方法。 本发明特别适用于避免包含识别码的区域的欺骗性重新编程。 本发明还涉及一种相关联的方法。

公开(公告)号：US06568510B2

公开(公告)日：2003-05-27

申请号：US09997214

申请日：2001-11-15

Applicant: Paola Cavaleri ,  Bruno Leconte ,  Sébastien Zink ,  Jean Devin

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sébastien Zink ,  Jean Devin

IPC: G11C1604

CPC classification number: G11C16/3418 ,  G11C16/10

Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

公开(公告)号：US06434056B1

公开(公告)日：2002-08-13

申请号：US09746473

申请日：2000-12-21

Applicant: Alessandro Brigati ,  Jean Devin ,  Bruno Leconte

Inventor： Alessandro Brigati ,  Jean Devin ,  Bruno Leconte

IPC: G11C700

Abstract: Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose role is to maintain the read or write operation of one microcontroller when another is selected.

公开(公告)号：US6011724A

公开(公告)日：2000-01-04

申请号：US980195

申请日：1997-11-26

Applicant: Alessandro Brigati ,  Jean Devin ,  Bruno LeConte

Inventor： Alessandro Brigati ,  Jean Devin ,  Bruno LeConte

IPC: G11C16/16 ,  G11C16/30 ,  G11C11/34

CPC classification number: G11C16/30 ,  G11C16/16 ,  H02M2001/0025

Abstract: A method for the erasure of a non-volatile and electrically erasable memory in which the amplitude of the pulses that are sent to erase the memory varies as a function of the number of pulses previously sent. A circuit for the generation of erasure pulses of variable amplitude for a non-volatile and electrically erasable memory.

Abstract translation: 用于擦除非易失性和电可擦除存储器的方法，其中发送到擦除存储器的脉冲的幅度随先前发送的脉冲数的函数而变化。 用于产生用于非易失性和电可擦除存储器的可变幅度的擦除脉冲的电路。

公开(公告)号：US5883833A

公开(公告)日：1999-03-16

申请号：US703811

申请日：1996-08-27

Applicant: David Naura ,  Jean Devin

Inventor： David Naura ,  Jean Devin

IPC: G11C16/12 ,  G11C16/14 ,  G11C11/34

CPC classification number: G11C16/14 ,  G11C16/12

Abstract: A method and apparatus for the programming and erasure of a memory cell made out of floating-gate transistors and to the circuit pertaining thereto is described. It can be applied especially to non-volatile electrically erasable and programmable memories, for example EEPROMs and flash EPROMs. A programming voltage or erasure voltage including a voltage shift equal in value to a reference voltage is produced, followed by a voltage ramp comprising a rising phase followed possibly by voltage plateau, this voltage ramp being shifted in voltage by the value of the reference voltage and being followed, in turn, by a voltage drop. The value of the voltage shift is fixed at an intermediate value that is lower than the value of a so-called tunnel voltage of the memory cell but greater than the supply voltage.

Abstract translation: 描述了由浮栅晶体管制成的存储单元的编程和擦除以及与其有关的电路的方法和装置。 它可以特别适用于非易失性电可擦除和可编程存储器，例如EEPROM和闪存EPROM。 产生包括与参考电压值相等的电压偏移的编程电压或擦除电压，随后是包括可能伴随电压平台的上升相的电压斜坡，该电压斜坡在电压上移动参考电压的值， 随之而来的是电压降。 电压偏移的值固定在比存储单元的所谓的隧道电压的值低的值的中间值，但大于电源电压。