公开(公告)号：US07693243B2

公开(公告)日：2010-04-06

申请号：US11235714

申请日：2005-09-26

Applicant: Tien-Hui Chen ,  Jeff Lin ,  Yi-Sheng Lin

Inventor： Tien-Hui Chen ,  Jeff Lin ,  Yi-Sheng Lin

IPC: H04L7/00

CPC classification number: H04L7/0004 ,  H04L7/0062

Abstract: A circuit and method for timing recovery. The circuit for timing recovery comprises an converter, a timing recovery controller, and a initial phase generator. The converter converts an input signal to sample data with a sampling signal. The timing recovery controller is coupled to the converter, and determines the sampling signal. And the initial phase generator is coupled to the AD converter, detects a change with the sample data only, produces an initial phase based on the change, and controls the sampling signal.

Abstract translation: 一种用于定时恢复的电路和方法。 用于定时恢复的电路包括转换器，定时恢复控制器和初始相位发生器。 转换器将采样信号的输入信号转换为采样数据。 定时恢复控制器耦合到转换器，并确定采样信号。 并且初始相位发生器耦合到AD转换器，仅检测采样数据的变化，根据变化产生初始相位，并控制采样信号。

公开(公告)号：US20090104804A1

公开(公告)日：2009-04-23

申请号：US11876838

申请日：2007-10-23

Applicant: Jeff Lin

Inventor： Jeff Lin

IPC: H01R4/58 ,  H05K3/10

CPC classification number: H05K3/202 ,  F21K9/00 ,  F21S43/14 ,  F21Y2107/00 ,  F21Y2115/10 ,  H05K1/0284 ,  H05K1/029 ,  H05K2201/09063 ,  H05K2201/10106 ,  H05K2201/10598 ,  H05K2203/175 ,  Y10T29/49155

Abstract: An LED interconnection apparatus and a method of electrical connection for an array of LEDs are disclosed, the LED interconnection apparatus including a back plate substrate having a plurality of adaptable through-holes formed therein and a flexible conductive pattern disposed adjacent the back plate substrate, wherein the adaptable through-holes of the back plate substrate facilitate selective access to the flexible conductive pattern to provide a simple, adaptable, and standardized method of electrical communication for an array of LEDs.

Abstract translation: 公开了一种用于LED阵列的LED互连装置和电连接方法，所述LED互连装置包括具有形成在其中的多个适应通孔的背板基板和邻近所述背板基板设置的柔性导电图案，其中， 背板基板的可适应的通孔有助于选择性地接近柔性导电图案，以提供用于LED阵列的简单，适应性和标准化的电通信方法。

公开(公告)号：US20080140743A1

公开(公告)日：2008-06-12

申请号：US11608459

申请日：2006-12-08

Applicant: Ying-Cheng Lee ,  Jeff Lin

Inventor： Ying-Cheng Lee ,  Jeff Lin

IPC: G06F17/00

CPC classification number: H03M13/4107

Abstract: An add-compare-select (ACS) unit generates first path metrics having a first bit-pair and a most significant bit-pair (MSB), where each bit-pair is in represented in redundant numbers comprising a high bit and a low bit, and comprises a first ACS circuit and an MSB ACS circuit. The first ACS circuit produces the first bit-pair of the first path metrics and a first carry. The MSB ACS circuit comprises a limiting circuit, an MSB maximum select unit, an MSB storage unit, and a reset unit. The limiting circuit, coupled to the first ACS circuit, generates the MSB of the first path metrics based on the first carry, and limits the MSB of the first path metrics to a first predetermined value. The MSB maximum select (MS) unit, coupled to the limiting circuit and another ACS unit, receives an MSB of second path metrics from the other ACS unit, and compares the MSBs of the first and the second path metrics to determine MSB decision signals based on maximum likelihood selection. The MSB storage unit, coupled to the MSB maximum select unit, stores the MSB of the first path metrics as an MSB of a previous first path metric. The reset unit, coupled to the MSB maximum select unit and the MSB storage unit, and resets the high bit of the MSB of the first path metrics to a second predetermined value when the high bits of the MSBs of the first and the second path metrics reach the first predetermined value.

Abstract translation: 加法比较选择（ACS）单元产生具有第一位对和最高有效位对（MSB）的第一路径量度，其中每个位对以冗余数表示，包括高位和低位 ，并且包括第一ACS电路和MSB ACS电路。 第一ACS电路产生第一路径度量的第一位对和第一进位。 MSB ACS电路包括限幅电路，MSB最大选择单元，MSB存储单元和复位单元。 耦合到第一ACS电路的限制电路基于第一进位产生第一路径度量的MSB，并将第一路径量度的MSB限制为第一预定值。 耦合到限制电路和另一个ACS单元的MSB最大选择（MS）单元从另一个ACS单元接收第二路径度量的MSB，并且比较第一和第二路径度量的MSB以确定基于MSB决策信号 最大似然选择。 耦合到MSB最大选择单元的MSB存储单元将第一路径度量的MSB存储为先前的第一路径度量的MSB。 复位单元，耦合到MSB最大选择单元和MSB存储单元，并且当第一和第二路径度量的MSB的高位时，将第一路径度量的MSB的高位重置为第二预定值 达到第一预定值。

公开(公告)号：US20070071152A1

公开(公告)日：2007-03-29

申请号：US11235714

申请日：2005-09-26

Applicant: Tien-Hui Chen ,  Jeff Lin ,  Yi-Sheng Lin

Inventor： Tien-Hui Chen ,  Jeff Lin ,  Yi-Sheng Lin

IPC: H04L7/00

CPC classification number: H04L7/0004 ,  H04L7/0062

Abstract: A circuit and method for timing recovery. The circuit for timing recovery comprises an converter, a timing recovery controller, and a initial phase generator. The converter converts an input signal to sample data with a sampling signal. The timing recovery controller is coupled to the converter, and determines the sampling signal. And the initial phase generator is coupled to the AD converter, detects a change with the sample data only, produces an initial phase based on the change, and controls the sampling signal.

Abstract translation: 一种用于定时恢复的电路和方法。 用于定时恢复的电路包括转换器，定时恢复控制器和初始相位发生器。 转换器将采样信号的输入信号转换为采样数据。 定时恢复控制器耦合到转换器，并确定采样信号。 并且初始相位发生器耦合到AD转换器，仅检测采样数据的变化，根据变化产生初始相位，并控制采样信号。

公开(公告)号：US20070066244A1

公开(公告)日：2007-03-22

申请号：US11229934

申请日：2005-09-19

Applicant: Kai-Pon Kao ,  Jeff Lin

Inventor： Kai-Pon Kao ,  Jeff Lin

IPC: H04B1/44 ,  H04B17/00

CPC classification number: H04B7/0808

Abstract: Method, system and apparatus for receiving antenna selection, comprising a receiving step, a determining step, an estimating step, and an assigning step. The receiving step involves receiving data and second data associated with a first antenna and a second antenna. It follows the determining step determining first and second throughputs with the first data and the second data. Next the estimating step estimating first signal deviance and second signal deviance between the received data (Dki) and a reference signal (Rki), with the first data and the second data respectively. Finally the assigning step assigning a receiving antenna among the first and the second antennas, based on the first and the second throughputs, and the first and the second signal deviances.

Abstract translation: 用于接收天线选择的方法，系统和装置，包括接收步骤，确定步骤，估计步骤和分配步骤。 接收步骤包括接收与第一天线和第二天线相关联的数据和第二数据。 遵循确定步骤，利用第一数据和第二数据确定第一和第二吞吐量。 接下来，估计步骤分别与第一数据和第二数据估计接收数据（Dki）和参考信号（Rki）之间的第一信号偏差和第二信号偏差。 最后，基于第一和第二吞吐量以及第一和第二信号偏差来分配在第一和第二天线之间的接收天线的分配步骤。

公开(公告)号：US20070064701A1

公开(公告)日：2007-03-22

申请号：US11229938

申请日：2005-09-19

Applicant: Jeff Lin ,  Jiun-Jang Su ,  You-Hu Yen

Inventor： Jeff Lin ,  Jiun-Jang Su ,  You-Hu Yen

IPC: H04L12/28

CPC classification number: H04W52/0238 ,  H04W8/26 ,  H04W40/00 ,  H04W84/12 ,  Y02D70/142

Abstract: A method and device receiving a WLAN signal in a receiver. The receiver comprises a receiving module and a controller module. The receiving module receives first data. The controller module coupled to the receiving module determines second data from the first data, and disables the receiving module if the second data does not correspond to identity information of the receiver.

Abstract translation: 一种在接收机中接收WLAN信号的方法和设备。 接收机包括接收模块和控制器模块。 接收模块接收第一个数据。 耦合到接收模块的控制器模块从第一数据确定第二数据，并且如果第二数据不对应于接收器的身份信息，则禁止接收模块。

公开(公告)号：US5878661A

公开(公告)日：1999-03-09

申请号：US114118

申请日：1998-07-13

Applicant: Andrew Zachary Glovatsky ,  Vivek Amir Jairazbhoy ,  Jeff Lin ,  John Trublowski

Inventor： Andrew Zachary Glovatsky ,  Vivek Amir Jairazbhoy ,  Jeff Lin ,  John Trublowski

IPC: B41N1/24 ,  H05K3/12 ,  B05C17/06

CPC classification number: H05K3/1225 ,  B41N1/24 ,  Y10T29/49169

Abstract: There is disclosed herein a self-shearing stencil for use in applying solder paste or other bonding material atop a printed circuit board (PCB) in a predefined pattern. The stencil 50 has a top surface 12, a bottom surface 14, a first surface cavity 16 in the top surface, and a second surface cavity 18 in the bottom surface proximate the first surface. The cavities 16/18 overlap in a predefined manner so as to be in open communication with each other. When the stencil is placed on the PCB, the cavities are filled with solder paste and the PCB is then lowered away from the stencil, whereupon a bottom ledge 26 (defined by the stencil material underneath the first cavity) shears off the solder paste in the first cavity from the paste in the second cavity.

Abstract translation: 这里公开了一种自剪切模板，用于以预定图案在印刷电路板（PCB）的顶部上施加焊膏或其它粘合材料。 模板50具有顶表面12，底表面14，顶表面中的第一表面空腔16和靠近第一表面的底表面中的第二表面腔18。 空腔16/18以预定的方式重叠，以便彼此开放连通。 当模板放置在PCB上时，空穴填充有焊膏，然后将PCB从模板上降下，然后将底部凸缘26（由第一腔下方的模板材料限定）在该模具中剪切出焊膏 第一腔从第二腔中的糊状物。