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公开(公告)号：US20140122929A1
公开(公告)日：2014-05-01
申请号：US13665719
申请日：2012-10-31
申请人： Scott P. Nixon , Eric M. Rentschler
发明人： Scott P. Nixon , Eric M. Rentschler
IPC分类号： G06F11/273
CPC分类号： G06F11/27 , G06F11/3065 , G06F11/348 , G06F11/3648 , G06F11/3656 , G06F2201/86
摘要： A method and apparatus for distributed on-chip debug triggering is presented. A first bus includes a plurality of lines and a debugging state machine configurable to monitor the plurality of lines of the first bus. One or more nodes are configurable to detect triggering events and provide, in response to detecting one or more triggering events, signals to the debugging state machine using a first subset of the plurality of lines that is allocated to the node(s).
摘要翻译： 提出了一种用于分布式片上调试触发的方法和装置。 第一总线包括多条线路和可配置为监视第一总线的多条线路的调试状态机。 一个或多个节点可配置为检测触发事件，并且响应于检测到一个或多个触发事件而使用分配给该节点的多条线路的第一子集向调试状态机提供信号。
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公开(公告)号：US08683265B2
公开(公告)日：2014-03-25
申请号：US12980842
申请日：2010-12-29
IPC分类号： G06F11/00
CPC分类号： G06F11/3632 , G01R31/31705 , G06F11/3656
摘要： An embodiment of an electronic system includes a first electronic module, a second electronic module, a first debug circuit integrated with the first electronic module, a second debug circuit integrated with the second electronic module, and a communications interface between the first debug circuit and the second debug circuit. The first debug circuit is configured to determine that a triggering event has occurred, and to produce a first cross trigger signal on the communications interface in response to determining that the triggering event has occurred. The second debug circuit is configured to detect the first cross trigger signal on the communications interface, and to perform an action in response to detecting the first cross trigger signal.
摘要翻译： 电子系统的实施例包括第一电子模块，第二电子模块，与第一电子模块集成的第一调试电路，与第二电子模块集成的第二调试电路，以及第一调试电路和第二调试电路之间的通信接口 第二调试电路。 第一调试电路被配置为响应于确定触发事件已经发生而确定触发事件已经发生，并且在通信接口上产生第一交叉触发信号。 第二调试电路被配置为检测通信接口上的第一交叉触发信号，并且响应于检测到第一交叉触发信号而执行动作。
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公开(公告)号：US20120146658A1
公开(公告)日：2012-06-14
申请号：US12980842
申请日：2010-12-29
IPC分类号： G01R31/02
CPC分类号： G06F11/3632 , G01R31/31705 , G06F11/3656
摘要： An embodiment of an electronic system includes a first electronic module, a second electronic module, a first debug circuit integrated with the first electronic module, a second debug circuit integrated with the second electronic module, and a communications interface between the first debug circuit and the second debug circuit. The first debug circuit is configured to determine that a triggering event has occurred, and to produce a first cross trigger signal on the communications interface in response to determining that the triggering event has occurred. The second debug circuit is configured to detect the first cross trigger signal on the communications interface, and to perform an action in response to detecting the first cross trigger signal.
摘要翻译： 电子系统的实施例包括第一电子模块，第二电子模块，与第一电子模块集成的第一调试电路，与第二电子模块集成的第二调试电路，以及第一调试电路和第二调试电路之间的通信接口 第二调试电路。 第一调试电路被配置为响应于确定触发事件已经发生而确定触发事件已经发生，并且在通信接口上产生第一交叉触发信号。 第二调试电路被配置为检测通信接口上的第一交叉触发信号，并且响应于检测到第一交叉触发信号而执行动作。
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公开(公告)号：US07289587B2
公开(公告)日：2007-10-30
申请号：US10830367
申请日：2004-04-22
IPC分类号： H04L7/04 , G06F13/14 , H03K19/0175
CPC分类号： G01R31/31704 , G01R31/31705 , G01R31/31717 , G01R31/31725
摘要： Systems, methods, and other embodiments associated with a repeatable communication system are disclosed. One example system for receiving signals from an electronic component over a plurality of point-to-point communication links comprises a repeatability logic operably connected to each of the plurality of point-to-point communication links and configured to apply a delay offset to the signals received to compensate for frequency changes in signal transmissions over the plurality of point-to-point communication links.
摘要翻译： 公开了与可重复通信系统相关联的系统，方法和其他实施例。 用于通过多个点对点通信链路从电子部件接收信号的一个示例系统包括可操作地连接到多个点对点通信链路中的每一个的重复性逻辑，并且被配置为对信号应用延迟偏移 被接收以补偿在多个点对点通信链路上的信号传输中的频率变化。
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公开(公告)号：US09129061B2
公开(公告)日：2015-09-08
申请号：US13557756
申请日：2012-07-25
申请人： Scott P. Nixon , Tiger Lu , Eric M. Rentschler
发明人： Scott P. Nixon , Tiger Lu , Eric M. Rentschler
IPC分类号： G06F11/36
CPC分类号： G06F11/364 , G06F11/3648
摘要： The present invention provides a method and apparatus for dynamically configuring debug triggering patterns. One example embodiment of the method includes comparing values of bits received on a first subset of a plurality of lines of a bus with a first pattern of bits and capturing values of bits received on a second subset of the plurality of lines of the bus in response to the comparison indicating that the values of the bits received on the first subset of the lines match the first pattern of bits. The exemplary embodiment of the method also includes defining a second pattern for triggering a debug action using the captured values.
摘要翻译： 本发明提供一种用于动态配置调试触发模式的方法和装置。 该方法的一个示例性实施例包括比较在总线的多条线路的第一子集上接收的比特值与第一比特模式，并响应于在总线的多条线路的第二子集上接收的比特值 比较指示在第一子集上接收的比特的值与第一种比特模式相匹配。 该方法的示例性实施例还包括使用捕获的值定义用于触发调试动作的第二模式。
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公开(公告)号：US09037911B2
公开(公告)日：2015-05-19
申请号：US13095627
申请日：2011-04-27
IPC分类号： G06F11/00 , G06F11/267 , G06F11/22
CPC分类号： G06F11/267 , G06F11/22
摘要： Embodiments include methods for performing various operations in a computing system that includes an electronic module and a debug circuit. The method includes programming the debug circuit to monitor for pre-selected triggers produced by the computing system, and to perform actions in response to detecting the pre-select triggers. For example, in response to various pre-selected triggers, the debug circuit may, among other things: perform state transitions and log information indicating whether or not the state transitions were performed; monitor various signals when the debug circuit has determined that a test escape has occurred; and/or perform one or more actions that initiate stopping one or more clocks in response to certain pre-selected triggers.
摘要翻译： 实施例包括用于在包括电子模块和调试电路的计算系统中执行各种操作的方法。 该方法包括对调试电路进行编程以监视由计算系统产生的预先选择的触发，并且响应于检测到预选触发而执行动作。 例如，响应于各种预先选择的触发，调试电路可以除其他之外：执行状态转换和指示状态转换是否被执行的日志信息; 当调试电路确定已经发生测试逃生时，监视各种信号; 和/或执行响应于某些预先选择的触发而启动停止一个或多个时钟的一个或多个动作。
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公开(公告)号：US20140047262A1
公开(公告)日：2014-02-13
申请号：US13572249
申请日：2012-08-10
申请人： Scott P. Nixon , Eric M. Rentschler
发明人： Scott P. Nixon , Eric M. Rentschler
IPC分类号： G06F1/12
CPC分类号： G06F11/3656 , G06F1/10 , G06F1/14 , G06F11/3636
摘要： An integrated circuit with multiple clock domain tracing capability includes a debug module including a global time stamp counter for counting pulses of a reference clock signal to provide a global time stamp, a first granularity counter for counting pulses of a first clock signal to provide a first granularity count, a second granularity counter fir counting pulses of a second clock signal to provide a second granularity count and a trace cache buffer for selectively storing in a first partition the global time stamp, the first granularity count, and first data synchronous to the first clock signal, and for selectively storing in a second partition the global time stamp, the second granularity count, and second data synchronous to the second clock signal.
摘要翻译： 具有多个时钟域跟踪功能的集成电路包括一个调试模块，包括一个用于计数参考时钟信号的脉冲以提供全局时间戳的全局时间戳计数器，第一粒度计数器，用于对第一时钟信号的脉冲进行计数以提供第一 粒度计数，第二粒度计数器计数第二时钟信号的脉冲以提供第二粒度计数，以及跟踪高速缓冲存储器，用于选择性地在第一分区中存储全局时间戳，第一粒度计数和与第一粒度同步的第一数据 时钟信号，并且用于在第二分区中选择性地存储与第二时钟信号同步的全局时间戳，第二粒度计数和第二数据。
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公开(公告)号：US06381663B1
公开(公告)日：2002-04-30
申请号：US09277718
申请日：1999-03-26
IPC分类号： G06F1300
CPC分类号： G06F13/1673 , G06F13/4059
摘要： An apparatus and method for permitting bus locking in a computer system having a mixed architecture. The mixed architecture includes a first bus coupled to processors that may run applications using bus locking or cache line locking. The apparatus interfaces the first bus with a second bus that does not support bus locking. The apparatus when presented with a locked transaction effectively implements bus locking on the second bus.
摘要翻译： 一种在具有混合架构的计算机系统中允许总线锁定的装置和方法。 混合架构包括耦合到处理器的第一总线，其可以使用总线锁定或高速缓存行锁定来运行应用。 该设备将第一总线与不支持总线锁定的第二总线接口。 该装置在呈现锁定事务时有效地在第二总线上实现总线锁定。
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29.发明授权Caching and coherency control of multiple geometry accelerators in a computer graphics system 失效计算机图形系统中多个几何加速器的缓存和一致性控制
公开(公告)号：US5969726A
公开(公告)日：1999-10-19
申请号：US866909
申请日：1997-05-30
CPC分类号： G06T15/005
摘要： A computer graphics system for rendering graphics primitives based upon primitive data received from a host computer through a graphics interface includes a plurality of geometry accelerators. A distributor divides the primitive data into chunks of primitive data and distributes the chunks to a current geometry accelerator recipient. A state controller is configured to store and resend selected primitive data to the geometry accelerators based upon whether one or more vertices of a graphics primitive are contained in more than one of the chunks of primitive data. Advantageously, this enables the computer graphics system to efficiently process primitive data while avoiding providing the geometry accelerators with an excessive amount of data than necessary for them to render the primitives. Specifically, the state controller includes in the selected primitive data vertex states which were sent to a previous current geometry accelerator recipient and which are required by the current geometry accelerator recipient to assemble at least a portion of the graphics primitive. In addition, the state controller resends the property states to the current geometry accelerator recipient when the currently-stored local state in the current geometry accelerator recipient is not the same as a currently-effective local state. Furthermore, when the resent vertex states include a first and second resent vertex state, the selected primitive data includes property states which changed from when the first vertex state was sent to the previous current geometry accelerator and the second vertex state was sent to the previous current geometry accelerator.
摘要翻译： 用于基于通过图形接口从主计算机接收的原始数据来渲染图形基元的计算机图形系统包括多个几何加速器。 分销商将原始数据划分成原始数据块，并将块分配给当前的几何加速器收件人。 状态控制器被配置为基于图形基元的一个或多个顶点是否包含在原始数据块中的多于一个的块中，将所选择的原始数据存储并重新发送到几何加速器。 有利地，这使得计算机图形系统能够有效地处理原始数据，同时避免向几何加速器提供比它们渲染图元所需的数据量过大的数据。 具体地说，状态控制器包括被选择的原始数据顶点状态，这些顶点状态被发送到先前的当前几何加速器接收者，并且当前的几何加速器接收者需要它来组装图形原语的至少一部分。 此外，当当前几何加速器收件人当前存储的本地状态与当前有效的本地状态不同时，状态控制器会将属性状态重新发送到当前几何加速器接收方。 此外，当重新发送的顶点状态包括第一和第二重新顶点状态时，所选择的原始数据包括从第一顶点状态被发送到先前的当前几何加速器而改变并且第二顶点状态被发送到先前电流的属性状态 几何加速器
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公开(公告)号：US5793660A
公开(公告)日：1998-08-11
申请号：US837189
申请日：1997-04-14
申请人： Eric M. Rentschler
发明人： Eric M. Rentschler
CPC分类号： G06F7/72
摘要： A circuit that finds m mod n may be obtained by creating the trial differences m-n, m-2n, m-3n, m-4n . . . , up to a limit determined by the sizes of m and n. The trial differences thus produced are examined in the order given to find the last one thereof that is non-negative. This examination involves only sign bits and a priority encoder. The magnitude portions of the various trial differences are applied as inputs to a first MUX whose selection is controlled by the priority encoder. The trial difference selected by the first MUX is applied as an input to a second MUX, whose other inputs are m itself, and zero. A separate initial comparison is performed between m and n, and controls what appears at the output of the second MUX. If n>m then the value of m appears at the output of the second MUX; if n=m or n=1 then zero appears; otherwise, m >n and it is the output from the first MUX that appears as the output of the second MUX. The output of the second MUX is m mod n. It can be shown that when m and n are powers of two (m=2.sup.u, n=2.sup.v), the most general case of interest is one where u.gtoreq.v, and that for such cases the number of trial differences that need to be formed is at most 2.sup.(u-1) -1.
摘要翻译： 可以通过产生试验差m-n，m-2n，m-3n，m-4n来获得m mod n的电路。 。 。 ，直到由m和n的大小确定的极限。 按照给出的顺序检查如此产生的试验差异，以找到非负的最后一个。 该检查仅涉及符号位和优先编码器。 将各种试验差异的大小部分作为输入施加到第一MUX，其选择由优先级编码器控制。 由第一MUX选择的试用差分作为输入施加到第二MUX，其另一个输入是m本身，并且为零。 在m和n之间进行单独的初始比较，并控制在第二个MUX的输出端出现的内容。 如果n> m，则m的值出现在第二MUX的输出端; 如果n = m或n = 1，则出现零; 否则，m> n，并且是作为第二MUX的输出出现的来自第一MUX的输出。 第二MUX的输出为m mod n。 可以表明，当m和n是二（m = 2u，n = 2v）的幂时，最常见的情况是u> / = v，而在这种情况下，需要的试验差异数 要形成的最多为2（u-1）-1。
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