公开(公告)号：US20050253626A1

公开(公告)日：2005-11-17

申请号：US11005890

申请日：2004-12-06

申请人： Yan Chong ,  Chiakang Sung ,  Bonnie Wang ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  In What Kim ,  Gopi Rangan ,  Tzung-Chin Chang ,  Surgey Shumarayev ,  Thomas White

发明人： Yan Chong ,  Chiakang Sung ,  Bonnie Wang ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  In What Kim ,  Gopi Rangan ,  Tzung-Chin Chang ,  Surgey Shumarayev ,  Thomas White

IPC分类号： G01R19/155 ,  G06F1/24 ,  G06F1/28 ,  G06F1/32 ,  H03K3/356 ,  H03K17/22 ,  H03K19/0175

CPC分类号： H03K3/356008 ,  G01R19/155 ,  G06F1/24 ,  G06F1/28 ,  G06F1/3203 ,  H03K17/223

摘要： A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.

公开(公告)号：US06714044B1

公开(公告)日：2004-03-30

申请号：US10106673

申请日：2002-03-25

申请人： Gopi Rangan ,  Khai Nguyen ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Yan Chong ,  Philip Pan ,  Joseph Huang ,  Bonnie Wang

发明人： Gopi Rangan ,  Khai Nguyen ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Yan Chong ,  Philip Pan ,  Joseph Huang ,  Bonnie Wang

IPC分类号： G06F738

CPC分类号： H03K19/17776 ,  G11C2207/104 ,  H03K19/17764

摘要： Techniques and circuitry are used to more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel via parallel inputs (705), and this data is also handled internally in parallel. The configuration data will be stored in a data register (722). This data register is segmented into two or more segments, each segment being made up of a serial chain of registers (808). The configuration data is input into the two of more segments of the data registers in parallel. Circuitry is also provided to handle redundancy.

摘要翻译： 技术和电路用于更快速地配置可编程集成电路。 配置数据通过并行输入（705）并行输入到可编程集成电路中，并且该数据也在内部并行处理。 配置数据将被存储在数据寄存器（722）中。 该数据寄存器被分割成两个或多个段，每个段由串行链路寄存器（808）组成。 配置数据并行输入数据寄存器的两个更多段。 还提供电路来处理冗余。

公开(公告)号：US06766505B1

公开(公告)日：2004-07-20

申请号：US10106675

申请日：2002-03-25

申请人： Gopi Rangan ,  Khai Nguyen ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Yan Chong ,  Philip Pan ,  Joseph Huang ,  Bonnie Wang

发明人： Gopi Rangan ,  Khai Nguyen ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Yan Chong ,  Philip Pan ,  Joseph Huang ,  Bonnie Wang

IPC分类号： G06F1750

CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/17764 ,  Y02T10/82

摘要： Techniques and circuitry are used to more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel via parallel inputs (705), and this data is also handled internally in parallel. The configuration data will be stored in a data register (722). This data register includes two or more serial register chains, each chain being made up of a serial chain of registers. The configuration data is input into the two of more chains of the data registers in parallel. Circuitry is also provided to handle redundancy.

摘要翻译： 技术和电路用于更快速地配置可编程集成电路。 配置数据通过并行输入（705）并行输入到可编程集成电路中，并且该数据也在内部并行处理。 配置数据将被存储在数据寄存器（722）中。 该数据寄存器包括两个或多个串行寄存器链，每个链由串行寄存器组成。 配置数据并行输入数据寄存器的两个链中。 还提供电路来处理冗余。

公开(公告)号：US07200769B1

公开(公告)日：2007-04-03

申请号：US10037861

申请日：2002-01-02

申请人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

发明人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

IPC分类号： G06F1/04

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/108 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091

摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.

摘要翻译： 用于延迟多数据速率接口的时钟信号的方法和装置。 一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。 还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。 第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。 第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

公开(公告)号：US07002384B1

公开(公告)日：2006-02-21

申请号：US10759915

申请日：2004-01-16

申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

IPC分类号： H03K5/13 ,  H03D3/24

CPC分类号： H03L7/0814 ,  H03L7/085 ,  H03L7/093

摘要： Phase comparators for use in loop circuits (i.e., DLL circuits and PLL circuits) are provided. The phase comparators include a phase detector for comparing a reference clock signal and a feedback signal derived from the loop circuit generated internal clock signal. The phase comparators also include a low-pass noise filter for filtering out erroneously detected phase differences between the reference clock signal and the feedback signal by requiring a certain net number of leading or lagging detections before the compensation circuitry of the loop circuit (i.e., the controlled delay line in a DLL circuit or the controlled oscillator in a PLL circuit) is adjusted. The number of net measurements required before these adjustments take place depends on a programmable bandwidth signal provided to the phase comparator.

摘要翻译： 提供了用于环路电路（即DLL电路和PLL电路）的相位比较器。 相位比较器包括用于比较参考时钟信号和从产生的环路电路生成的内部时钟信号导出的反馈信号的相位检测器。 相位比较器还包括低通噪声滤波器，用于通过在环路电路的补偿电路之前需要一定的净数量的前导或滞后检测来滤除参考时钟信号和反馈信号之间的错误检测的相位差（即， 调节DLL电路中的受控延迟线或PLL电路中的受控振荡器）。 在进行这些调整之前所需的净测量数取决于提供给相位比较器的可编程带宽信号。

公开(公告)号：US07725755B1

公开(公告)日：2010-05-25

申请号：US11668353

申请日：2007-01-29

申请人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

发明人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

IPC分类号： G06F1/00 ,  G06F1/14

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/108 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091

摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.

摘要翻译： 用于延迟多数据速率接口的时钟信号的方法和装置。 一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。 还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。 第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。 第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

公开(公告)号：US07205806B2

公开(公告)日：2007-04-17

申请号：US11181366

申请日：2005-07-13

申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

IPC分类号： H03K5/13 ,  H03D3/24

CPC分类号： H03L7/0814 ,  H03L7/085 ,  H03L7/093

摘要： Phase comparators for use in loop circuits (i.e., DLL circuits and PLL circuits) are provided. The phase comparators include a phase detector for comparing a reference clock signal and a feedback signal derived from the loop circuit generated internal clock signal. The phase comparators also include a low-pass noise filter for filtering out erroneously detected phase differences between the reference clock signal and the feedback signal by requiring a certain net number of leading or lagging detections before the compensation circuitry of the loop circuit (i.e., the controlled delay line in a DLL circuit or the controlled oscillator in a PLL circuit) is adjusted. The number of net measurements required before these adjustments take place depends on a programmable bandwidth signal provided to the phase comparator.

摘要翻译： 提供了用于环路电路（即DLL电路和PLL电路）的相位比较器。 相位比较器包括用于比较参考时钟信号和从产生的环路电路生成的内部时钟信号导出的反馈信号的相位检测器。 相位比较器还包括低通噪声滤波器，用于通过在环路电路的补偿电路之前需要一定的净数量的前导或滞后检测来滤除参考时钟信号和反馈信号之间的错误检测的相位差（即， 调节DLL电路中的受控延迟线或PLL电路中的受控振荡器）。 在进行这些调整之前所需的净测量数取决于提供给相位比较器的可编程带宽信号。

公开(公告)号：US20060164139A1

公开(公告)日：2006-07-27

申请号：US11181366

申请日：2005-07-13

申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/085 ,  H03L7/093

摘要： Phase comparators for use in loop circuits (i.e., DLL circuits and PLL circuits) are provided. The phase comparators include a phase detector for comparing a reference clock signal and a feedback signal derived from the loop circuit generated internal clock signal. The phase comparators also include a low-pass noise filter for filtering out erroneously detected phase differences between the reference clock signal and the feedback signal by requiring a certain net number of leading or lagging detections before the compensation circuitry of the loop circuit (i.e., the controlled delay line in a DLL circuit or the controlled oscillator in a PLL circuit) is adjusted. The number of net measurements required before these adjustments take place depends on a programmable bandwidth signal provided to the phase comparator.

公开(公告)号：US07212054B1

公开(公告)日：2007-05-01

申请号：US11479660

申请日：2006-06-29

申请人： Tzung-chin Chang ,  Chiakang Sung ,  Yan Chong ,  Henry Kim ,  Joseph Huang

发明人： Tzung-chin Chang ,  Chiakang Sung ,  Yan Chong ,  Henry Kim ,  Joseph Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0805

摘要： Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector and an up down counter that provides a main control signal to adjust the delay by the main variable delay circuit. When the DLL circuit is locked, an arithmetic logic unit (ALU) produces a processed control signal based on the main control signal, an ALU control signal and an offset control signal, and the processed control signal is provided to the smaller variable delay circuit. By adjusting the ALU control and offset control signals, the phase shift introduced on the DLL control signal by the smaller variable delay circuit can be adjusted. In another embodiment of the invention, a second up down counter is used in place of an ALU for providing a dynamically adjustable phase shift in accordance with the principles of the present invention.

摘要翻译： 描述了用于使用处理的控制信号产生具有可调相移的DLL时钟信号的电路和方法。 在本发明的一个实施例中，提供一种DLL电路，其包括主要和较小的可变延迟电路，相位检测器和向上计数器，其提供主控制信号以通过主可变延迟电路来调整延迟。 当DLL电路被锁定时，算术逻辑单元（ALU）基于主控制信号，ALU控制信号和偏移控制信号产生处理的控制信号，并且处理的控制信号被提供给较小的可变延迟电路。 通过调整ALU控制和偏移控制信号，可以调整由较小的可变延迟电路引入到DLL控制信号上的相移。 在本发明的另一实施例中，根据本发明的原理，使用第二向上计数器来代替ALU来提供动态可调的相移。

公开(公告)号：US07091760B1

公开(公告)日：2006-08-15

申请号：US10788221

申请日：2004-02-25

申请人： Tzung-chin Chang ,  Chiakang Sung ,  Yan Chong ,  Henry Kim ,  Joseph Huang

发明人： Tzung-chin Chang ,  Chiakang Sung ,  Yan Chong ,  Henry Kim ,  Joseph Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0805

摘要： Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector and an up down counter that provides a main control signal to adjust the delay by the main variable delay circuit. When the DLL circuit is locked, an arithmetic logic unit (ALU) produces a processed control signal based on the main control signal, an ALU control signal and an offset control signal, and the processed control signal is provided to the smaller variable delay circuit. By adjusting the ALU control and offset control signals, the phase shift introduced on the DLL control signal by the smaller variable delay circuit can be adjusted. In another embodiment of the invention, a second up down counter is used in place of an ALU for providing a dynamically adjustable phase shift in accordance with the principles of the present invention.

摘要翻译： 描述了用于使用处理的控制信号产生具有可调相移的DLL时钟信号的电路和方法。 在本发明的一个实施例中，提供一种DLL电路，其包括主要和较小的可变延迟电路，相位检测器和向上计数器，其提供主控制信号以通过主可变延迟电路来调整延迟。 当DLL电路被锁定时，算术逻辑单元（ALU）基于主控制信号，ALU控制信号和偏移控制信号产生处理的控制信号，并且处理的控制信号被提供给较小的可变延迟电路。 通过调整ALU控制和偏移控制信号，可以调整由较小的可变延迟电路引入到DLL控制信号上的相移。 在本发明的另一实施例中，根据本发明的原理，使用第二向上计数器来代替ALU来提供动态可调的相移。