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121 条记录 (耗时 0.034 秒)

    Memory device including 3-dimensionally arranged memory cell transistors and methods of operating the same
    21.
    发明授权
    Memory device including 3-dimensionally arranged memory cell transistors and methods of operating the same 有权
    包括三维布置的存储单元晶体管的存储器件及其操作方法

    公开(公告)号：US07701771B2

    公开(公告)日：2010-04-20

    申请号：US11882769

    申请日：2007-08-06

    申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Hoo-Sung Cho

    发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Hoo-Sung Cho

    IPC分类号： G11C11/03

    CPC分类号： H01L27/115 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551

    摘要： A memory device may include L semiconductor layers, a gate structure on each of the semiconductor layers, N bitlines, and/or a common source line on each of the semiconductor layers. The L semiconductor layers may be stacked, and/or L may be an integer greater than 1. The N bitlines may be on the gate structures and crossing over the gate structures, and/or N may be an integer greater than 1. Each of the common source lines may be connected to each other such that the common source lines have equipotentiality with each other.

    摘要翻译： 存储器件可以包括L个半导体层，每个半导体层上的栅极结构，N个位线和/或每个半导体层上的公共源极线。 L个半导体层可以被堆叠，和/或L可以是大于1的整数.N个位线可以在栅极结构上并且跨过栅极结构，和/或N可以是大于1的整数。 公共源极线可以彼此连接，使得公共源极线彼此具有等电位。

    Body-tied-to-source MOSFETs with asymmetrical source and drain regions and methods of fabricating the same
    23.
    发明申请
    Body-tied-to-source MOSFETs with asymmetrical source and drain regions and methods of fabricating the same 有权
    具有不对称源极和漏极区域的体耦对源MOSFET及其制造方法

    公开(公告)号：US20060049467A1

    公开(公告)日：2006-03-09

    申请号：US11179236

    申请日：2005-07-12

    申请人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hun Jeong

    发明人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hun Jeong

    IPC分类号： H01L27/01

    CPC分类号： H01L29/0847 ,  H01L21/743 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78612 ,  H01L29/78654

    摘要： A metal oxide semiconductor field effect transistor (MOSFET) includes a body pattern of a first conductivity type disposed on an insulating layer. A gate electrode is disposed on the body pattern. A drain region of a second conductivity type is disposed on the insulating layer and having a sidewall in contact with a first sidewall of the body pattern. An impurity-doped region of the first conductivity type is disposed on the insulating layer and having a sidewall in contact with a second sidewall of the body pattern. The MOSFET further includes a source region of the second conductivity type disposed on the impurity-doped region and having a sidewall in contact with the second sidewall of the body pattern, and a contact plug extending through the source region to contact the impurity-doped region.

    摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）包括设置在绝缘层上的第一导电类型的主体图案。 栅电极设置在主体图案上。 第二导电类型的漏极区域设置在绝缘层上并且具有与主体图案的第一侧壁接触的侧壁。 第一导电类型的杂质掺杂区域设置在绝缘层上并且具有与主体图案的第二侧壁接触的侧壁。 MOSFET还包括设置在杂质掺杂区域上并具有与主体图案的第二侧壁接触的侧壁的第二导电类型的源极区域，以及延伸穿过源极区域以接触杂质掺杂区域的接触插塞 。

    METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING METALLIZATION COMPRISING SELECT LINES, BIT LINES AND WORD LINES
    24.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING METALLIZATION COMPRISING SELECT LINES, BIT LINES AND WORD LINES 有权
    形成包含选择线，位线和字线的金属化的半导体器件的方法

    公开(公告)号：US20120009767A1

    公开(公告)日：2012-01-12

    申请号：US13236000

    申请日：2011-09-19

    申请人： Young-Chul JANG ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    发明人： Young-Chul JANG ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    IPC分类号： H01L21/20

    CPC分类号： H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

    摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。

    Methods of forming SRAM devices having buried layer patterns
    25.
    发明授权
    Methods of forming SRAM devices having buried layer patterns 有权
    形成具有埋层图案的SRAM器件的方法

    公开(公告)号：US08048727B2

    公开(公告)日：2011-11-01

    申请号：US12687545

    申请日：2010-01-14

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

    IPC分类号： H01L21/00

    CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

    摘要： An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

    摘要翻译： SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

    MULTI-LAYER MEMORY DEVICES
    26.
    发明申请
    MULTI-LAYER MEMORY DEVICES 有权
    多层存储器件

    公开(公告)号：US20110163411A1

    公开(公告)日：2011-07-07

    申请号：US13049495

    申请日：2011-03-16

    申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L27/08

    CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

    摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

    Semiconductor device and method for forming the same
    27.
    发明申请
    Semiconductor device and method for forming the same 有权
    半导体装置及其形成方法

    公开(公告)号：US20080067517A1

    公开(公告)日：2008-03-20

    申请号：US11655115

    申请日：2007-01-19

    申请人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    发明人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    IPC分类号： H01L29/772 ,  H01L21/8234

    CPC分类号： H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

    摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。

    Methods of forming semiconductor devices having self-aligned bodies
    28.
    发明授权
    Methods of forming semiconductor devices having self-aligned bodies 失效
    形成具有自对准体的半导体器件的方法

    公开(公告)号：US08084306B2

    公开(公告)日：2011-12-27

    申请号：US12409968

    申请日：2009-03-24

    申请人： Jae-Hun Jeong ,  Hoon Lim ,  Soon-Moon Jung ,  Hoo-Sung Cho

    发明人： Jae-Hun Jeong ,  Hoon Lim ,  Soon-Moon Jung ,  Hoo-Sung Cho

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/783 ,  H01L29/78606 ,  H01L29/78654

    摘要： A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.

    摘要翻译： 半导体器件包括具有源极区域，漏极区域，插入在源极区域和漏极区域之间的沟道区域的主体区域以及从沟道区域的端部延伸的主体区域延伸部。 在沟道区域和体区域上形成栅极图案，并且体接触将栅极图案连接到身体区域。 身体区域延伸部的侧壁与栅极图案的侧壁自对准。 还公开了具有自对准体和身体接触的半导体器件的形成方法。

    METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING SELF-ALIGNED BODIES
    29.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING SELF-ALIGNED BODIES 失效
    形成具有自对准体的半导体器件的方法

    公开(公告)号：US20090181511A1

    公开(公告)日：2009-07-16

    申请号：US12409968

    申请日：2009-03-24

    申请人： Jae Hun Jeong ,  Hoon Lim ,  Soon-Moon Jung ,  Hoo-Sung Cho

    发明人： Jae Hun Jeong ,  Hoon Lim ,  Soon-Moon Jung ,  Hoo-Sung Cho

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/783 ,  H01L29/78606 ,  H01L29/78654

    摘要： A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.

    摘要翻译： 半导体器件包括具有源极区域，漏极区域，插入在源极区域和漏极区域之间的沟道区域的主体区域以及从沟道区域的端部延伸的主体区域延伸部。 在沟道区域和体区域上形成栅极图案，并且体接触将栅极图案连接到身体区域。 身体区域延伸部的侧壁与栅极图案的侧壁自对准。 还公开了具有自对准体和身体接触的半导体器件的形成方法。

    Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines
    30.
    发明授权
    Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines 有权
    用于形成具有包括选择线，位线和字线的金属化的半导体器件的方法

    公开(公告)号：US08399308B2

    公开(公告)日：2013-03-19

    申请号：US13236000

    申请日：2011-09-19

    申请人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    发明人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    IPC分类号： H01L21/82

    CPC分类号： H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

    摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。