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    Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines
    1.
    发明授权
    Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines 有权
    用于形成具有包括选择线，位线和字线的金属化的半导体器件的方法

    公开(公告)号：US08399308B2

    公开(公告)日：2013-03-19

    申请号：US13236000

    申请日：2011-09-19

    申请人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    发明人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    IPC分类号： H01L21/82

    CPC分类号： H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

    摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。

    Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines
    2.
    发明申请
    Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines 失效
    用于形成具有包括选择线，位线和字线的金属化的半导体器件的方法

    公开(公告)号：US20100035386A1

    公开(公告)日：2010-02-11

    申请号：US12588240

    申请日：2009-10-08

    申请人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    发明人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    IPC分类号： H01L21/768

    CPC分类号： H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

    摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。

    METHODS OF FABRICATING MULTI-LAYER NONVOLATILE MEMORY DEVICES
    3.
    发明申请
    METHODS OF FABRICATING MULTI-LAYER NONVOLATILE MEMORY DEVICES 有权
    制造多层非易失性存储器件的方法

    公开(公告)号：US20090253257A1

    公开(公告)日：2009-10-08

    申请号：US12478538

    申请日：2009-06-04

    申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L21/8246 ,  H01L21/4763 ,  H01L21/3205

    CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

    摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

    Transistor and method of fabricating the same
    5.
    发明授权
    Transistor and method of fabricating the same 有权
    晶体管及其制造方法

    公开(公告)号：US07563683B2

    公开(公告)日：2009-07-21

    申请号：US11611719

    申请日：2006-12-15

    申请人： Young-Chul Jang ,  Won-Seok Cho ,  Soon-Moon Jung

    发明人： Young-Chul Jang ,  Won-Seok Cho ,  Soon-Moon Jung

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66787 ,  H01L21/76224 ,  H01L27/10876

    摘要： Disclosed is a method for fabricating a gate of a field effect transistor. The method comprises a) forming a field oxide layer on a silicon substrate and then applying a photoresist layer in order to define a gate, b) etching the silicon substrate using the photoresist layer as a mask, c) sequentially depositing a gate oxide layer and a gate polysilicon layer on an entire surface of the silicon substrate and defining the gate using the photoresist layer, d) etching the resulting silicon substrate using the photoresist layer as a mask to form the gate and forming an N− ion region by means of ion implantation, and e) depositing and etching back an oxide layer to form a sidewall oxide layer and forming an N+ ion region by means of ion implantation. Consequently, the gate is made by etching the silicon substrate. Thus, a length of the gate is reduced, so that it is possible not only to make a cell area smaller but also to prevent a short-channel effect.

    摘要翻译： 公开了一种用于制造场效应晶体管的栅极的方法。 该方法包括：a）在硅衬底上形成场氧化物层，然后施加光致抗蚀剂层以限定栅极，b）使用光致抗蚀剂层作为掩模蚀刻硅衬底，c）依次沉积栅极氧化物层和 在硅衬底的整个表面上的栅极多晶硅层，并使用光致抗蚀剂层限定栅极; d）使用光致抗蚀剂层作为掩模蚀刻所得到的硅衬底，以形成栅极并通过离子形成N-离子区域 注入，以及e）沉积和蚀刻回氧化物层以形成侧壁氧化物层，并通过离子注入形成N +离子区域。 因此，通过蚀刻硅衬底来制造栅极。 因此，栅极的长度减小，使得不仅可以使单元区域更小，而且可以防止短沟道效应。

    TRANSISTOR AND METHOD OF FABRICATING THE SAME
    6.
    发明申请
    TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
    晶体管及其制造方法

    公开(公告)号：US20070087491A1

    公开(公告)日：2007-04-19

    申请号：US11611719

    申请日：2006-12-15

    申请人： Young-Chul Jang ,  Won-Seok Cho ,  Soon-Moon Jung

    发明人： Young-Chul Jang ,  Won-Seok Cho ,  Soon-Moon Jung

    IPC分类号： H01L21/84 ,  H01L21/00

    CPC分类号： H01L29/66787 ,  H01L21/76224 ,  H01L27/10876

    摘要： Disclosed is a method for fabricating a gate of a field effect transistor. The method comprises a) forming a field oxide layer on a silicon substrate and then applying a photoresist layer in order to define a gate, b) etching the silicon substrate using the photoresist layer as a mask, c) sequentially depositing a gate oxide layer and a gate polysilicon layer on an entire surface of the silicon substrate and defining the gate using the photoresist layer, d) etching the resulting silicon substrate using the photoresist layer as a mask to form the gate and forming an N− ion region by means of ion implantation, and e) depositing and etching back an oxide layer to form a sidewall oxide layer and forming an N+ ion region by means of ion implantation. Consequently, the gate is made by etching the silicon substrate. Thus, a length of the gate is reduced, so that it is possible not only to make a cell area smaller but also to prevent a short-channel effect.

    摘要翻译： 公开了一种用于制造场效应晶体管的栅极的方法。 该方法包括：a）在硅衬底上形成场氧化物层，然后施加光致抗蚀剂层以限定栅极，b）使用光致抗蚀剂层作为掩模蚀刻硅衬底，c）依次沉积栅极氧化物层和 在硅衬底的整个表面上的栅极多晶硅层，并使用光致抗蚀剂层限定栅极; d）使用光致抗蚀剂层作为掩模蚀刻所得的硅衬底，以形成栅极并形成N + >离子区域，以及e）通过离子注入沉积和蚀刻回氧化物层以形成侧壁氧化物层并形成N + +离子区域。 因此，通过蚀刻硅衬底来制造栅极。 因此，栅极的长度减小，使得不仅可以使单元区域更小，而且可以防止短沟道效应。

    Method for manufacturing semiconductor device
    7.
    发明授权
    Method for manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US5740065A

    公开(公告)日：1998-04-14

    申请号：US449853

    申请日：1995-05-24

    申请人： Young-Chul Jang ,  Hyo-Seok Choi ,  Dong-Heui Jang ,  Sun-Yong Lee

    发明人： Young-Chul Jang ,  Hyo-Seok Choi ,  Dong-Heui Jang ,  Sun-Yong Lee

    IPC分类号： H01L21/02 ,  G03F7/20 ,  G03F9/00 ,  H01L21/68 ,  G01B11/26 ,  G06F17/18

    CPC分类号： G03F7/70633 ,  G03F9/7046

    摘要： A method for manufacturing a semiconductor device comprises the steps of extracting an optimal working condition by accumulatively averaging accumulated working conditions of lots previously performed in an expectation process to be currently performed in the manufacturing equipment, extracting a correction condition by extracting information for an alignment state of a lower layer performed by the expectation process, and setting the working condition by adding the correction condition to the optimal working condition.

    摘要翻译： 一种制造半导体器件的方法，包括以下步骤：通过对在制造设备中当前执行的预期处理中先前执行的批量的累积工作条件累积平均来提取最佳工作条件，通过提取校准状态的信息来提取校正条件 通过预期处理执行的下层，并且通过将校正条件添加到最佳工作条件来设定工作条件。

    Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines
    8.
    发明授权
    Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines 失效
    用于形成具有包括选择线，位线和字线的金属化的半导体器件的方法

    公开(公告)号：US08034668B2

    公开(公告)日：2011-10-11

    申请号：US12588240

    申请日：2009-10-08

    申请人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    发明人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    IPC分类号： H01L21/76

    CPC分类号： H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

    摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。

    Methods of fabricating multi-layer nonvolatile memory devices
    9.
    发明授权
    Methods of fabricating multi-layer nonvolatile memory devices 有权
    制造多层非易失性存储器件的方法

    公开(公告)号：US07910433B2

    公开(公告)日：2011-03-22

    申请号：US12478538

    申请日：2009-06-04

    申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/84

    CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

    摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。