公开(公告)号：US20100123505A1

公开(公告)日：2010-05-20

申请号：US12273365

申请日：2008-11-18

Applicant: Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu

Inventor： Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu

IPC: H03L5/00

CPC classification number: H03K3/356113 ,  H03K3/356182

Abstract: A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH.

Abstract translation: 公开了一种具有内部低压电源（VCCL）和外部高压电源（VCCH）的集成电路系统的电压电平移动电路，电压电平移位电路包括一对连接到VCCH的交叉耦合PMOS晶体管 ，具有连接到地（VSS）的源极和连接到在VCCL和VSS之间摆动的第一信号的栅极的NMOS晶体管，以及耦合在第一PMOS晶体管的漏极和第一PMOS晶体管的漏极之间的第一阻断装置 NMOS晶体管，所述第一阻断装置被配置为当所述第一信号处于静态或者从逻辑高电平转换到逻辑低电平时导通有源电流，并且所述第一阻断装置被配置为当所述第一信号从 逻辑低电平为逻辑高电平。

公开(公告)号：US20050212527A1

公开(公告)日：2005-09-29

申请号：US10810383

申请日：2004-03-26

Applicant: Jui-Jen Wu

Inventor： Jui-Jen Wu

IPC: G01R31/02 ,  G01R31/07 ,  G11C17/16 ,  G11C29/02 ,  H02H7/00

CPC classification number: G11C29/02 ,  G01R31/07 ,  G11C17/16 ,  G11C29/027

Abstract: A fuse detection circuit has; a fuse (102) under detection to produce a first voltage in the first arm in response to a read signal; a reference fuse (108) to produce a second voltage in response to the read signal; a sensing circuit (124) to sense the first voltage and the second voltage as status value data of the fuse under detection; a latch circuit (136) to keep the data in the sensing circuit; and a timing control circuit (138) to turn off the fuse bridge circuit independently of the read signal.

Abstract translation: 保险丝检测电路具有： 检测到的熔丝（102），以响应于读取信号在第一臂中产生第一电压; 参考熔丝（108），用于响应于读取信号产生第二电压; 感测电路（124），用于感测第一电压和第二电压作为被检测的熔丝的状态值数据; 锁存电路（136），用于将数据保持在感测电路中; 以及定时控制电路（138），以独立于读取信号来关断熔丝桥电路。

公开(公告)号：US08358165B2

公开(公告)日：2013-01-22

申请号：US13308035

申请日：2011-11-30

Applicant: Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu

Inventor： Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu

IPC: H03L5/00

CPC classification number: H03K3/356113 ,  H03K3/356182

Abstract: A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor. The voltage level shifter further includes a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, such that the voltage level shifter can operate at a lower VCCL.

Abstract translation: 具有内部低电压电源（VCCL）和外部高压电源（VCCH）的电压电平移位器包括：第一PMOS晶体管和第二PMOS晶体管，每个PMOS晶体管和第二PMOS晶体管的源极连接到VCCH，第一PMOS晶体管的栅极 耦合到第二PMOS晶体管的漏极，并且第二PMOS晶体管的栅极耦合到第一PMOS晶体管的漏极。 电压电平移位器还包括第一NMOS晶体管，源极连接到地（VSS），栅极连接到在VCCL和VSS之间摆动的第一信号，以及耦合在第一PMOS晶体管的漏极之间的第一阻断装置 以及第一NMOS晶体管的漏极，使得电压电平移位器可以在较低VCCL下工作。

公开(公告)号：US20120306537A1

公开(公告)日：2012-12-06

申请号：US13308035

申请日：2011-11-30

Applicant: Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu

Inventor： Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu

IPC: H03K19/0175

CPC classification number: H03K3/356113 ,  H03K3/356182

Abstract: A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor. The voltage level shifter further includes a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, such that the voltage level shifter can operate at a lower VCCL.

Abstract translation: 具有内部低电压电源（VCCL）和外部高压电源（VCCH）的电压电平移位器包括：第一PMOS晶体管和第二PMOS晶体管，每个PMOS晶体管和第二PMOS晶体管的源极连接到VCCH，第一PMOS晶体管的栅极 耦合到第二PMOS晶体管的漏极，并且第二PMOS晶体管的栅极耦合到第一PMOS晶体管的漏极。 电压电平移位器还包括第一NMOS晶体管，源极连接到地（VSS），栅极连接到在VCCL和VSS之间摆动的第一信号，以及耦合在第一PMOS晶体管的漏极之间的第一阻断装置 以及第一NMOS晶体管的漏极，使得电压电平移位器可以在较低VCCL下工作。

公开(公告)号：US08179735B2

公开(公告)日：2012-05-15

申请号：US12732931

申请日：2010-03-26

Applicant: Jui-Jen Wu

Inventor： Jui-Jen Wu

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C7/08 ,  G11C7/18 ,  G11C8/14 ,  G11C11/413 ,  G11C2207/002 ,  G11C2207/005

Abstract: In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers the data on the local bit line to a global bit line. A neighbor global bit line is used as a reference for a global sense amplifier to read the differential data on the global bit line and the neighbor global bit line.

Abstract translation: 在与存储器单元中读取数据相关的一些实施例中，数据被驱动到驱动局部读出放大器的局部位线。 根据存储器单元中的数据的逻辑电平以及局部位线，局部读出放大器将局部位线上的数据传送到全局位线。 相邻全局位线用作全局读出放大器的参考，以读取全局位线和邻近全局位线上的差分数据。

公开(公告)号：US08144501B2

公开(公告)日：2012-03-27

申请号：US12345125

申请日：2008-12-29

Applicant: Yen-Huei Chen ,  Jui-Jen Wu

Inventor： Yen-Huei Chen ,  Jui-Jen Wu

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7855

Abstract: An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a gate of the pull-up transistor, and a back-gate decoupled from the front gate.

Abstract translation: 集成电路结构包括静态随机存取存储器（SRAM）单元。 SRAM单元包括上拉晶体管和下拉晶体管，其形成具有上拉晶体管的反相器。 下拉晶体管包括连接到上拉晶体管的栅极的前栅极和从前栅极去耦的后栅极。

公开(公告)号：US07466581B2

公开(公告)日：2008-12-16

申请号：US11713280

申请日：2007-03-02

Applicant: Huai-Ying Huang ,  Yen-Huei Chen ,  Jui-Jen Wu ,  Ping-Wei Wang

Inventor： Huai-Ying Huang ,  Yen-Huei Chen ,  Jui-Jen Wu ,  Ping-Wei Wang

IPC: G11C11/00

CPC classification number: G11C11/413

Abstract: An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other.

公开(公告)号：US20080212353A1

公开(公告)日：2008-09-04

申请号：US11713280

申请日：2007-03-02

Applicant: Huai-Ying Huang ,  Yen-Huei Chen ,  Jui-Jen Wu ,  Ping-Wei Wang

Inventor： Huai-Ying Huang ,  Yen-Huei Chen ,  Jui-Jen Wu ,  Ping-Wei Wang

IPC: G11C5/06

CPC classification number: G11C11/413

Abstract: An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other.

Abstract translation: 布置在多行和多列中的静态随机存取存储器（SRAM）单元的阵列包括连接到SRAM单元的VSS节点的多条VSS线，每条VSS线连接到同一列中的SRAM单元 。 多个VSS线包括连接到SRAM单元的第一列的第一VSS线; 以及连接到所述SRAM单元的第二列的第二VSS线，其中所述第一和第二VSS线彼此断开。

公开(公告)号：US20130107609A1

公开(公告)日：2013-05-02

申请号：US13284532

申请日：2011-10-28

Applicant: Meng-Fan Chang ,  Lai-Fu Chen ,  Jui-Jen Wu ,  Hiroyuki Yamauchi

Inventor： Meng-Fan Chang ,  Lai-Fu Chen ,  Jui-Jen Wu ,  Hiroyuki Yamauchi

IPC: G11C11/40

CPC classification number: G11C11/412

Abstract: A static random access memory cell comprising a first inverter, a second inverter, a first transistor, a second transistor, and a third transistor. The first inverter is cross-coupled with the second inverter. The first transistor is connected with a write word line, a write bit line, and a first output node of the first inverter. The second transistor is connected with a complementary write bit line, the write word line, and a second output node of the second inverter. The third transistor is connected with a read bit line, a read word line, and the first input node of the first inverter to form a read port transistor, and a read port is formed. The read port transistor has a feature of asymmetric threshold voltage, and the read bit line swing can be expanded by the decrease of clamping current or the boosted read bit line.

Abstract translation: 一种静态随机存取存储单元，包括第一反相器，第二反相器，第一晶体管，第二晶体管和第三晶体管。 第一个反相器与第二个反相器交叉耦合。 第一晶体管与第一反相器的写字线，写位线和第一输出节点连接。 第二晶体管与第二反相器的互补写位线，写字线和第二输出节点连接。 第三晶体管与读位线，读字线和第一反相器的第一输入节点连接，形成读端口晶体管，形成读端口。 读端口晶体管具有不对称阈值电压的特征，并且可以通过钳位电流或升压读位线的减小来扩展读位线摆幅。

公开(公告)号：US08174867B2

公开(公告)日：2012-05-08

申请号：US12617437

申请日：2009-11-12

Applicant: Jui-Jen Wu

Inventor： Jui-Jen Wu

IPC: G11C11/00

CPC classification number: G11C11/413 ,  G11C5/145 ,  G11C11/412

Abstract: An integrated circuit structure includes a static random access memory (SRAM) cell; a first power supply node connected to the SRAM cell, wherein the first power supply node is configured to provide a first positive power supply voltage to the SRAM cell; and a bit-line connected to the SRAM cell. A negative-voltage generator is coupled to, and configured to output a negative voltage to, the bit-line, wherein the negative-voltage generator is so configured that the negative voltage decreases in response to a decrease in the first positive power supply voltage and increases in response to an increase in the first positive supply voltage.

Abstract translation: 集成电路结构包括静态随机存取存储器（SRAM）单元; 连接到所述SRAM单元的第一电源节点，其中所述第一电源节点被配置为向所述SRAM单元提供第一正电源电压; 以及连接到SRAM单元的位线。 负电压发生器被耦合到位线并且被配置为向位线输出负电压，其中负电压发生器被配置成使得负电压响应于第一正电源电压的减小而减小，以及 响应于第一正电源电压的增加而增加。