公开(公告)号：US20230284464A1

公开(公告)日：2023-09-07

申请号：US17939859

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Hidehiro SHIGA ,  Daisaburo TAKASHIMA

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  H01L27/22 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L27/249 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/004 ,  G11C13/0069 ,  H01L27/228 ,  H01L27/2454 ,  H01L43/02 ,  H01L45/126 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79

Abstract: According to a certain embodiment, the 3D stacked semiconductor memory includes: a first electrode line extending in a first direction orthogonal to the semiconductor substrate; a second electrode line adjacent to the first electrode line in a second direction orthogonal to the first direction, and extending in the first direction; a first variable resistance film extending in the first direction and in contact with the second electrode line; a first semiconductor film in contact with the first variable resistance film and the first electrode line; a first potential applying electrode extending in the second direction and in contact with a first insulator layer; a second semiconductor film in contact with a second variable resistance film and the first electrode line; and a second potential applying electrode extending in the second direction and in contact with a second insulator layer. The first and second potential applying electrodes are electrically different nodes.

公开(公告)号：US20220189556A1

公开(公告)日：2022-06-16

申请号：US17399548

申请日：2021-08-11

Applicant: Kioxia Corporation

Inventor： Kazutaka IKEGAMI ,  Hidehiro SHIGA

IPC: G11C16/10 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/04

Abstract: A semiconductor storage device includes a first word line, a second word line provided in the same layer with the first word line and configured to be controlled independently from the first word line, a plurality of memory pillars between the first word line and the second word line, each of the plurality of memory pillars including a first memory cell facing to the first word line and a second memory cell facing to the second word line, the plurality of memory pillars being arranged in a first direction and a second direction intersecting to the first direction and a control circuit. The control circuit is configured to perform a write operation to the second memory cell included in the plurality of memory pillars after performing a write operation to the first memory cell included in each of the plurality of memory pillars.

公开(公告)号：US20220093152A1

公开(公告)日：2022-03-24

申请号：US17201114

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Reika TANAKA ,  Masumi SAITOH ,  Takashi MAEDA ,  Rieko FUNATSUKI ,  Hidehiro SHIGA

IPC: G11C11/22 ,  H01L27/11597

Abstract: According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.