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公开(公告)号:US11733888B2
公开(公告)日:2023-08-22
申请号:US17028087
申请日:2020-09-22
Applicant: Kioxia Corporation
Inventor: Shunichi Igahara , Toshikatsu Hida , Riki Suzuki , Takehiko Amaki , Suguru Nishikawa , Yoshihisa Kojima
CPC classification number: G06F3/0634 , G06F3/061 , G06F3/0604 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F12/0253 , G06F12/10 , G06F2212/1044 , G06F2212/657
Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.
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公开(公告)号:US11342026B2
公开(公告)日:2022-05-24
申请号:US17018147
申请日:2020-09-11
Applicant: Kioxia Corporation
Inventor: Suguru Nishikawa , Takehiko Amaki , Yoshihisa Kojima , Shunichi Igahara
Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.
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公开(公告)号:US11309051B2
公开(公告)日:2022-04-19
申请号:US17022274
申请日:2020-09-16
Applicant: Kioxia Corporation
Inventor: Shohei Asami , Takehiko Amaki
Abstract: According to one embodiment, a memory system includes: a memory chip including a first memory block and first word lines, the first memory block including a first memory string which includes first memory cells that are coupled in series, the first word lines being respectively coupled to gates of the first memory cells; a memory controller coupled to an external device, controlling the memory chip, and capable of performing an error checking and correcting process of data. When a write instruction is received from the external device, the memory controller is configured to perform a write operation on a second memory cell which is one of the first memory cells, and to perform a read verify operation including a read process and the ECC process on a third memory cell which is one of the first memory cells.
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公开(公告)号:US11194656B2
公开(公告)日:2021-12-07
申请号:US16774609
申请日:2020-01-28
Applicant: KIOXIA CORPORATION
Inventor: Shunichi Igahara , Yoshihisa Kojima , Takehiko Amaki , Suguru Nishikawa
Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.
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