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    Memory system and memory system control method
    1.
    发明授权
    Memory system and memory system control method 有权

    公开(公告)号：US11954357B2

    公开(公告)日：2024-04-09

    申请号：US17468895

    申请日：2021-09-08

    Applicant: Kioxia Corporation

    Inventor： Takehiko Amaki ,  Shunichi Igahara ,  Toshikatsu Hida ,  Yoshihisa Kojima ,  Riki Suzuki

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0679

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.

    Memory system
    3.
    发明授权
    Memory system 有权

    公开(公告)号：US11086718B2

    公开(公告)日：2021-08-10

    申请号：US16806131

    申请日：2020-03-02

    Applicant: KIOXIA CORPORATION

    Inventor： Riki Suzuki ,  Toshikatsu Hida ,  Yoshihisa Kojima ,  Takehiko Amaki ,  Suguru Nishikawa

    IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06

    Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

    Memory system and memory control method
    4.
    发明授权
    Memory system and memory control method 有权

    公开(公告)号：US11727998B2

    公开(公告)日：2023-08-15

    申请号：US17512394

    申请日：2021-10-27

    Applicant: KIOXIA CORPORATION

    Inventor： Shigehiro Asano ,  Neil Buxton ,  Julien Margetts ,  Shunichi Igahara ,  Takehiko Amaki

    IPC: G11C16/26 ,  G11C16/34 ,  G11C8/12 ,  G11C16/04

    CPC classification number: G11C16/3431 ,  G11C8/12 ,  G11C16/26 ,  G11C16/3495 ,  G11C16/0483

    Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.

    Semiconductor memory medium and memory system
    7.
    发明授权
    Semiconductor memory medium and memory system 有权

    公开(公告)号：US11615851B2

    公开(公告)日：2023-03-28

    申请号：US17572279

    申请日：2022-01-10

    Applicant: Kioxia Corporation

    Inventor： Suguru Nishikawa ,  Takehiko Amaki ,  Yoshihisa Kojima ,  Shunichi Igahara

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

    Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

    Memory system having memory device and controller
    8.
    发明授权
    Memory system having memory device and controller 有权

    公开(公告)号：US11422746B2

    公开(公告)日：2022-08-23

    申请号：US17002173

    申请日：2020-08-25

    Applicant: Kioxia Corporation

    Inventor： Suguru Nishikawa ,  Yoshihisa Kojima ,  Takehiko Amaki

    IPC: G06F12/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

    Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.

    Storage device, storage system, and control method
    9.
    发明授权
    Storage device, storage system, and control method 有权

    公开(公告)号：US12293106B2

    公开(公告)日：2025-05-06

    申请号：US17447088

    申请日：2021-09-08

    Applicant: Kioxia Corporation

    Inventor： Takehiko Amaki ,  Shunichi Igahara ,  Toshikatsu Hida ,  Yoshihisa Kojima

    IPC: G06F3/06

    Abstract: According to one embodiment, a storage device comprises a nonvolatile memory, and a controller configured to perform a first data write operation in a first mode, and to perform a second data write operation in a second mode. Data of a first number of bits is written per memory cell in the first mode. Data of a second number of bits is written per memory cell in the second mode. The second number is larger than the first number. The controller reserves one or more free blocks as write destination block candidates of the first data write operation, perform the first data write operation for one of the write destination block candidates, and perform a garbage collection.

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