公开(公告)号：US08953628B2

公开(公告)日：2015-02-10

申请号：US13154413

申请日：2011-06-06

申请人： David T. Hass

发明人： David T. Hass

IPC分类号： H04L12/28 ,  H04L12/931 ,  H04J1/16 ,  G06F12/08

CPC分类号： H04L49/00 ,  G06F12/0813 ,  H04L49/30

摘要： A processor includes a plurality of processor cores, a networking output, and a packet ordering device. The packet ordering device determines an ordering for packets that are processed by the processor cores. The packets are released to the networking output in a determined order.

摘要翻译： 处理器包括多个处理器核心，联网输出和分组排序设备。 分组排序设备确定处理器核心处理的分组的顺序。 数据包以确定的顺序被释放到网络输出。

公开(公告)号：US08037224B2

公开(公告)日：2011-10-11

申请号：US11831887

申请日：2007-07-31

申请人： Julianne Jiang Zhu ,  David T. Hass

发明人： Julianne Jiang Zhu ,  David T. Hass

IPC分类号： G06F13/42 ,  G06F13/00 ,  G06F13/14 ,  G06F15/75

CPC分类号： G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20100318703A1

公开(公告)日：2010-12-16

申请号：US12815092

申请日：2010-06-14

申请人： Julianne Jiang Zhu ,  David T. Hass

发明人： Julianne Jiang Zhu ,  David T. Hass

IPC分类号： G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20090058693A1

公开(公告)日：2009-03-05

申请号：US11849166

申请日：2007-08-31

申请人： Robert William Laker ,  David T. Hass

发明人： Robert William Laker ,  David T. Hass

IPC分类号： H03M7/40

CPC分类号： H03M7/40 ,  H03M7/3086

摘要： An apparatus to implement Huffman decoding in an INFLATE process in a compression engine. An embodiment of the apparatus includes a bit buffer, a set of comparators, and a lookup table. The bit buffer stores a portion of a compressed data stream. The set of comparators compares the portion of the compressed data stream with a plurality of predetermined values. The lookup table stores a plurality of LZ77 code segments and out puts one of the LZ77 code segments corresponding to an index at least partially derived from a comparison result from the set of comparators.

摘要翻译： 一种用于在压缩引擎中的INFLATE过程中实现霍夫曼解码的装置。 该装置的实施例包括位缓冲器，一组比较器和查找表。 比特缓冲器存储压缩数据流的一部分。 比较器组将压缩数据流的部分与多个预定值进行比较。 查找表存储多个LZ77代码段，并且输出与来自该比较器组的比较结果至少部分地导出的索引相对应的LZ77代码段中的一个。

公开(公告)号：US20080216074A1

公开(公告)日：2008-09-04

申请号：US11961910

申请日：2007-12-20

申请人： David T. Hass ,  Basab Mukherjee

发明人： David T. Hass ,  Basab Mukherjee

IPC分类号： G06F9/54 ,  G06F9/46 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/1036 ,  G06F12/0813 ,  H04L49/00

摘要： An advanced, processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个多线程处理器核心，每个处理器核心具有数据高速缓存和指令高速缓存。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20080184008A1

公开(公告)日：2008-07-31

申请号：US12019576

申请日：2008-01-24

申请人： Julianne Jiang Zhu ,  David T. Hass

发明人： Julianne Jiang Zhu ,  David T. Hass

IPC分类号： G06F15/76 ,  G06F9/02

CPC分类号： G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging net work is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息网络工作耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20080140956A1

公开(公告)日：2008-06-12

申请号：US12018144

申请日：2008-01-22

申请人： David T. Hass ,  Basab Mukherjee

发明人： David T. Hass ,  Basab Mukherjee

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F12/1036 ,  G06F12/0813 ,  H04L49/00

摘要： An advanced, processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

公开(公告)号：US09128771B1

公开(公告)日：2015-09-08

申请号：US12633702

申请日：2009-12-08

申请人： Gaurav Garg ,  David T. Hass

发明人： Gaurav Garg ,  David T. Hass

IPC分类号： G06F9/46 ,  G06F15/16 ,  G06F9/50

CPC分类号： G06F9/5083 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5027 ,  G06F9/505 ,  G06F9/5088 ,  G06F9/546 ,  G06F2209/548

摘要： A system, method, and computer program product are provided for sending a message from a first queue to a second queue associated with a receiver agent in response to a request. In operation, a message is sent from a sender agent to a first queue. Additionally, a request is received at the first queue from a receiver agent. Furthermore, the message is sent from the first queue to a second queue associated with the receiver agent, in response to the request.

摘要翻译： 提供了系统，方法和计算机程序产品，用于响应于请求将消息从第一队列发送到与接收方代理相关联的第二队列。 在操作中，消息从发送方代理发送到第一个队列。 另外，从接收方代理处接收到第一个队列的请求。 此外，响应于该请求，将消息从第一队列发送到与接收方代理相关联的第二队列。

公开(公告)号：US08725919B1

公开(公告)日：2014-05-13

申请号：US13164319

申请日：2011-06-20

申请人： Julianne J. Zhu ,  David T. Hass

发明人： Julianne J. Zhu ,  David T. Hass

IPC分类号： G06F13/00

CPC分类号： G06F9/4411 ,  G06F13/102 ,  G06F2213/0026 ,  G06F2213/0058

摘要： Disclosed is an approach for configuring devices for a multiprocessor system, where the devices pertaining to the different processors are viewed as connecting to a standardized common bus. Regardless of the specific processor to which a device is directly connected, that device can be generally identified and accessed along the standardized common bus. PCIe is an example of a suitable standardized bus type that can be employed, where the devices for each processor node are represented as PCIe devices. Therefore, each of the devices would appear to the system software as a PCIe device. A PCIe controller can then be used to access the device by referring to the appropriate device identifier. This permits any device to be accessed on any of the processor nodes, without separate and individualized configurations or drivers for each separate processor node.

摘要翻译： 公开了一种用于配置用于多处理器系统的设备的方法，其中属于不同处理器的设备被视为连接到标准化公共总线。 无论设备直接连接到哪个特定处理器，该设备一般可以通过标准化的公共总线进行识别和访问。 PCIe是可以采用的合适的标准总线类型的示例，其中用于每个处理器节点的设备被表示为PCIe设备。 因此，每个设备将作为PCIe设备出现在系统软件中。 然后可以使用PCIe控制器通过参考适当的设备标识符来访问设备。 这允许在任何处理器节点上访问任何设备，而对于每个单独的处理器节点没有单独和个性化的配置或驱动程序。

公开(公告)号：US08499302B2

公开(公告)日：2013-07-30

申请号：US13226384

申请日：2011-09-06

申请人： David T. Hass

发明人： David T. Hass

IPC分类号： G06F9/46 ,  G06F13/00 ,  G06F15/16 ,  G06F15/167 ,  H04L12/56

CPC分类号： H04L49/15 ,  G06F12/0813

摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。