公开(公告)号：US06987983B2

公开(公告)日：2006-01-17

申请号：US10396361

申请日：2003-03-26

申请人： Masao Kondo ,  Katsuyoshi Washio ,  Masatada Horiuchi

发明人： Masao Kondo ,  Katsuyoshi Washio ,  Masatada Horiuchi

IPC分类号： H04M1/00 ,  H05K1/00

CPC分类号： H01L27/0629 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The purpose of this invention is to realize a radio frequency monolithic integrated circuit high in performance, small in size and low in cost, where transistors and passive elements are arranged on a chip in which a conductive silicon substrate functions as a ground. Since the electromagnetic fields of passive elements induce a current in a conductive silicon substrate, a loss due to generation of Joule heat or the like occurs to lead to deterioration of the performance of the passive elements. To solve this problem, an SOI layer comprising a semiconductor layer having a large thickness and a high resistivity and a conductive silicon substrate is used, and passive elements and an active element are formed on the same substrate. Alternatively, a cavity is provided in the conductive substrate directly beneath the SOI layer in the region where the passive elements are formed, thereby attaining the object.

摘要翻译： 本发明的目的是实现高性能，小尺寸和低成本的射频单片集成电路，其中晶体管和无源元件布置在其中导电硅衬底用作接地的芯片上。 由于无源元件的电磁场在导电硅衬底中引起电流，所以发生由于焦耳热等的产生而导致的无源元件性能的恶化。 为了解决这个问题，使用包括具有大厚度和高电阻率的半导体层和导电硅衬底的SOI层，并且在同一衬底上形成无源元件和有源元件。 或者，在形成无源元件的区域中的SOI层的正下方的导电性基板中设置有空穴，从而实现该目的。

公开(公告)号：US06462364B1

公开(公告)日：2002-10-08

申请号：US09743238

申请日：2001-01-05

申请人： Masatada Horiuchi

发明人： Masatada Horiuchi

IPC分类号： H01L2976

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A semiconductor integrated circuit according to the present invention comprises a MOS transistor formed on an SOI substrate and a subsidiary transistor provided between a body node and a drain node of the MOS transistor and sharing a gate electrode with the MOS transistor, whereby body potential of the MOS transistor is controlled by gate and drain potentials. Accumulated body charge in a non-conducting state in the semiconductor integrated circuit is extracted by a resistor formed between the body node and a source, whereby various phenomena caused by floating body effect are eliminated. Since the body potential of the MOS transistor can be varied without creating an undesirable leakage current path, and hence without limitations to supplied voltage, its threshold voltage can be made variable so as to follow change in an input signal, thereby making it possible to achieve higher speed and lower voltage operation of the semiconductor integrated circuit. According to the present invention, it is possible to eliminate floating body effect, which is the greatest problem with an SOI transistor formed on an SOI substrate, and also to achieve lower voltage and greater current operation of a transistor without posing limitations to supplied voltage and without causing the problem of leakage current.

摘要翻译： 根据本发明的半导体集成电路包括形成在SOI衬底上的MOS晶体管和设置在MOS晶体管的体节点和漏极节点之间的辅助晶体管，并且与MOS晶体管共享栅极电极， MOS晶体管由栅极和漏极电位控制。 在半导体集成电路中的非导通状态下的累积体电荷由形成在体节点与源极之间的电阻器提取，由此消除由浮体效应引起的各种现象。 由于可以改变MOS晶体管的体电位而不产生不期望的漏电流路径，并且因此不限于所提供的电压，所以其阈值电压可以变化以跟随输入信号的变化，从而可以实现 半导体集成电路的更高速度和更低的电压操作。 根据本发明，可以消除作为在SOI衬底上形成的SOI晶体管的最大问题的浮体效应，并且还可以实现对晶体管的较低的电压和更大的电流操作，而不会限制供电电压， 而不会引起漏电流的问题。

公开(公告)号：US06329238B1

公开(公告)日：2001-12-11

申请号：US09716244

申请日：2000-11-21

申请人： Ken Yamaguchi ,  Shinichiro Kimura ,  Masatada Horiuchi ,  Tatsuya Teshima

发明人： Ken Yamaguchi ,  Shinichiro Kimura ,  Masatada Horiuchi ,  Tatsuya Teshima

IPC分类号： H01L218242

CPC分类号： H01L27/10808 ,  H01L27/10873

摘要： In a semiconductor memory device such as a DRAM, a conductive film is arranged on the rim portion of a isolation insulating film in opposition to a semiconductor substrate with a thin insulating film in between. This conductive film is electrically connected to a lower electrode of a storage capacitor. This novel arrangement can control the location of electrical pn junction independently of the location of metallurgical pn junction, thereby realizing a semiconductor memory device having a long data retention time with the increase in leakage current suppressed.

摘要翻译： 在诸如DRAM的半导体存储器件中，导电膜布置在隔离绝缘膜的边缘部分上，与半导体衬底相对，其间具有薄的绝缘膜。 该导电膜与存储电容器的下电极电连接。 这种新颖的布置可以独立于冶金pn结的位置来控制电pn结的位置，从而实现了抑制泄漏电流增加的数据保持时间长的半导体存储器件。

公开(公告)号：US4949151A

公开(公告)日：1990-08-14

申请号：US100232

申请日：1987-09-23

申请人： Masatada Horiuchi ,  Katsuyoshi Washio ,  Tohru Nakamura

发明人： Masatada Horiuchi ,  Katsuyoshi Washio ,  Tohru Nakamura

IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L23/485 ,  H01L27/082 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

CPC分类号： H01L29/66272 ,  H01L21/743 ,  H01L23/485 ,  H01L27/0823 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/456 ,  H01L2924/0002

摘要： A high integration bipolar transistor operable at very high operating speed is disclosed. A semiconductor device of this invention has a semiconductor substrate of a first conductivity type, a buried impurity region formed on the substrate, and a bipolar transistor formed on the buried impurity region, wherein a plurality of monocrystalline active regions defined by the buried impurity region are isolated from each other by an element isolation insulator, the buried impurity region is connected to a graft region formed on the element isolation insulator at least at the side wall of the buried impurity region, and connected to a semiconductor element in a different active region via the graft region.

摘要翻译： 公开了以非常高的工作速度工作的高集成度双极晶体管。 本发明的半导体器件具有第一导电类型的半导体衬底，形成在衬底上的掩埋杂质区域和形成在掩埋杂质区域上的双极晶体管，其中由掩埋杂质区域限定的多个单晶有源区域是 通过元件隔离绝缘体彼此隔离，所述掩埋杂质区至少在所述掩埋杂质区的侧壁处连接到形成在所述元件隔离绝缘体上的移植区域，并且经由所述掩模杂质区域连接到不同有源区域中的半导体元件 移植区域。

公开(公告)号：US4769686A

公开(公告)日：1988-09-06

申请号：US63785

申请日：1987-06-19

申请人： Masatada Horiuchi ,  Ken Yamaguchi

发明人： Masatada Horiuchi ,  Ken Yamaguchi

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/2257 ,  H01L21/823835 ,  H01L27/0927 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66628

摘要： Herein disclosed is a semiconductor device, especially, an MISFET which can ensure a high breakdown voltage and operate at a high speed. The semiconductor device according to the present invention reduces the sheet resistance by using an impurity region, which has an impurity concentration not exceeding 10.sup.20 cm.sup.-3, in a drain or source region and by forming a metal silicide layer on the surface of the impurity region. Moreover, the semiconductor device of the present invention is constructed such that the impurity concentration of an n-type drain or source region does not exceed 10.sup.20 cm.sup.-3 whereas the impurity concentration of a p-type drain or source region does not exceed 10.sup.19 cm.sup.-3 and such that at least one portion of the drain or source region is made of a metal silicide so that it can effectively protect the latch-up phenomenon which is caused when two or more semiconductor devices of different conductive type are integrated.

摘要翻译： 这里公开的是半导体器件，特别是能够确保高击穿电压并以高速运行的MISFET。 根据本发明的半导体器件通过在漏极或源极区域中使用杂质浓度不超过1020cm -3的杂质区域并且在杂质区域的表面上形成金属硅化物层来降低薄层电阻 。 此外，本发明的半导体器件被构造成使得n型漏极或源极区域的杂质浓度不超过1020cm -3，而p型漏极或源极区域的杂质浓度不超过1019cm -3，并且使得漏极或源极区域的至少一部分由金属硅化物制成，使得其可以有效地保护当两个或更多个不同导电类型的半导体器件集成时引起的闩锁现象。

公开(公告)号：US06800513B2

公开(公告)日：2004-10-05

申请号：US10299793

申请日：2002-11-20

申请人： Masatada Horiuchi ,  Takashi Takahama

发明人： Masatada Horiuchi ,  Takashi Takahama

IPC分类号： H01L2100

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78648

摘要： A high performance super-minituarized double gate SOIMOS being fabricated by re-distributing the impurity with high concentration at the interface of a buried gate insulative film and by aligning the double gate in a self-aligned manner and furthermore, by isolating completely the buried gate electrodes electrically from each other, in which a multi-layered SOI substrate having an amorphous or polycrystal semiconductor layer constituted by way of a buried gate insulative film to a lower portion of an SOI layer is used, ion implantation is applied to the semiconductor layer in a pattern opposite to the upper gate electrode and the buried gate is constituted in a self-alignment relation with the upper gate.

摘要翻译： 通过在掩埋栅极绝缘膜的界面处重新分配杂质并通过自对准方式对准双栅极而制造高性能超分层双栅极SOIMOS，此外，通过完全隔离掩埋栅极 电极彼此电连接，其中使用具有通过掩埋栅极绝缘膜构成到SOI层的下部的非晶或多晶半导体层的多层SOI衬底，将离子注入施加到半导体层 与上栅极和掩埋栅极相对的图案以与上栅极的自对准关系构成。

公开(公告)号：US06781202B2

公开(公告)日：2004-08-24

申请号：US10303884

申请日：2002-11-26

申请人： Ken Yamaguchi ,  Yoshiaki Takemura ,  Kenichi Osada ,  Masatada Horiuchi ,  Takashi Uchino

发明人： Ken Yamaguchi ,  Yoshiaki Takemura ,  Kenichi Osada ,  Masatada Horiuchi ,  Takashi Uchino

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1083

摘要： A higher-performance short channel MOS transistor with enhanced resistance to soft errors caused by exposure to high-energy rays is realized. At the time of forming a deep source/drain diffusion layer region at high density, an intermediate region of a density higher than that of impurity of a semiconductor substrate is formed between the source/drain diffusion layer and the semiconductor substrate of a conduction type opposite to that of the source/drain diffusion layer. The intermediate region is formed with a diffusion window for forming the source/drain, an intermediate layer of uniform concentration and uniform width can be realized at low cost.

摘要翻译： 实现了通过暴露于高能射线引起的对软误差的增强的抗性的更高性能的短通道MOS晶体管。 在以高密度形成深源极/漏极扩散层区域时，在源极/漏极扩散层与相反的导电类型的半导体衬底之间形成密度高于半导体衬底的密度的中间区域 与源极/漏极扩散层的相反。 中间区形成有用于形成源极/漏极的扩散窗口，可以以低成本实现均匀浓度和均匀宽度的中间层。

公开(公告)号：US06730964B2

公开(公告)日：2004-05-04

申请号：US10260656

申请日：2002-10-01

申请人： Masatada Horiuchi

发明人： Masatada Horiuchi

IPC分类号： H01L2701

CPC分类号： H01L29/78612 ,  H01L21/84 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11803 ,  H01L27/1203

摘要： A semiconductor device has a MOSFET formed on a single crystalline silicon layer in an SOI structure in which the silicon layer is laminated along with an insulator on a handle wafer. To prevent the body floating effect, a recombination center region is formed connecting to the lower surfaces of source and drain regions of the MOSFET. Consequently, the holes generated within the single crystalline silicon layer just beneath a channel of the MOSFET are injected into the recombination center region by way of the single crystalline silicon layer beneath the source diffusion region and eliminated so that the body floating effect is prevented.

摘要翻译： 半导体器件具有形成在SOI结构中的单晶硅层上的MOSFET，其中硅层与处理晶片上的绝缘体层叠。 为了防止身体浮动效应，形成连接到MOSFET的源极和漏极区域的下表面的复合中心区域。 因此，刚好在MOSFET的通道正下方的单晶硅层内产生的空穴通过源极扩散区域下方的单晶硅层被注入到复合中心区域，并被消除，从而防止了浮体效应。

公开(公告)号：US06538268B1

公开(公告)日：2003-03-25

申请号：US09381399

申请日：1999-09-20

申请人： Masatada Horiuchi

发明人： Masatada Horiuchi

IPC分类号： H01L29772

CPC分类号： H01L29/78612 ,  H01L21/84 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11803 ,  H01L27/1203

摘要： A semiconductor device has a MOSFET formed on a single crystalline silicon layer in an SOI structure in which the silicon layer is laminated along with an insulator on a handle wafer. To prevent the body floating effect, a recombination center region is formed connecting to the lower surfaces of source and drain regions of the MOSFET. Consequently, the holes generated within the single crystalline silicon layer just beneath a channel of the MOSFET are injected into the recombination center region by way of the single crystalline silicon layer beneath the source diffusion region and eliminated so that the body floating effect is prevented.

公开(公告)号：US5227660A

公开(公告)日：1993-07-13

申请号：US648309

申请日：1991-01-29

申请人： Masatada Horiuchi ,  Kazuo Nakazato

发明人： Masatada Horiuchi ,  Kazuo Nakazato

IPC分类号： H01L27/102 ,  H01L27/108

CPC分类号： H01L27/10841 ,  H01L27/1023

摘要： This invention relates to a semiconductor device, in which a singlecrystal semiconductor substrate whose principal surface is a (111) plane is etched from the principal surface thereof in the direction perpendicular thereto to form a vertical trench and a lateral trench is formed at the bottom portion of the side wall of the vertical trench by effecting an anisotropic etching with respect to crystallographical axes so that the etching proceeds in the direction of axis, the lateral and the vertical trenches being filled with polycrystalline or amorphous semiconductor or insulator.

摘要翻译： 本发明涉及一种半导体器件，其中主表面为（111）面的单晶半导体衬底从其主表面沿与其垂直的方向蚀刻以形成垂直沟槽，并且横向沟槽形成在底部 通过相对于晶体轴进行各向异性蚀刻使垂直沟槽的侧壁沿<110>轴的方向进行，横向和垂直沟槽被多晶或非晶半导体或绝缘体填充。