公开(公告)号：US06987983B2

公开(公告)日：2006-01-17

申请号：US10396361

申请日：2003-03-26

申请人： Masao Kondo ,  Katsuyoshi Washio ,  Masatada Horiuchi

发明人： Masao Kondo ,  Katsuyoshi Washio ,  Masatada Horiuchi

IPC分类号： H04M1/00 ,  H05K1/00

CPC分类号： H01L27/0629 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The purpose of this invention is to realize a radio frequency monolithic integrated circuit high in performance, small in size and low in cost, where transistors and passive elements are arranged on a chip in which a conductive silicon substrate functions as a ground. Since the electromagnetic fields of passive elements induce a current in a conductive silicon substrate, a loss due to generation of Joule heat or the like occurs to lead to deterioration of the performance of the passive elements. To solve this problem, an SOI layer comprising a semiconductor layer having a large thickness and a high resistivity and a conductive silicon substrate is used, and passive elements and an active element are formed on the same substrate. Alternatively, a cavity is provided in the conductive substrate directly beneath the SOI layer in the region where the passive elements are formed, thereby attaining the object.

摘要翻译： 本发明的目的是实现高性能，小尺寸和低成本的射频单片集成电路，其中晶体管和无源元件布置在其中导电硅衬底用作接地的芯片上。 由于无源元件的电磁场在导电硅衬底中引起电流，所以发生由于焦耳热等的产生而导致的无源元件性能的恶化。 为了解决这个问题，使用包括具有大厚度和高电阻率的半导体层和导电硅衬底的SOI层，并且在同一衬底上形成无源元件和有源元件。 或者，在形成无源元件的区域中的SOI层的正下方的导电性基板中设置有空穴，从而实现该目的。

公开(公告)号：US06313012B1

公开(公告)日：2001-11-06

申请号：US09303080

申请日：1999-04-30

申请人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

发明人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

IPC分类号： H01L2130

CPC分类号： H01L27/1203 ,  H01L21/84 ,  Y10S438/977

摘要： Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate. The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

摘要翻译： 公开了一种多层SOI衬底，其包括支撑衬底和层叠在支撑衬底的主表面上的第一绝缘体，半导体膜，第二绝缘体和单晶半导体膜（SOI膜）。 SOI衬底通过直接接合技术形成，并且使用单晶半导体膜（SOI层）形成双极晶体管和MOS晶体管。 可以在没有外延生长的情况下形成极浅的结，从而以低成本显着提高半导体器件的操作速度。

公开(公告)号：US6004865A

公开(公告)日：1999-12-21

申请号：US612647

申请日：1996-03-08

申请人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

发明人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L21/331 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/84 ,  Y10S438/977

摘要： Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

摘要翻译： 公开了一种多层SOI衬底，其包括支撑衬底和层叠在支撑衬底的主表面上的第一绝缘体，半导体膜，第二绝缘体和单晶半导体膜（SOI膜）。SOI 通过直接接合技术形成衬底，并且使用单晶半导体膜（SOI层）形成双极晶体管和MOS晶体管。 可以在没有外延生长的情况下形成极浅的结，从而以低成本显着提高半导体器件的操作速度。

公开(公告)号：US5237200A

公开(公告)日：1993-08-17

申请号：US833759

申请日：1992-02-11

申请人： Mitsuo Nanba ,  Tohru Nakamura ,  Nakazato Kazuo ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

发明人： Mitsuo Nanba ,  Tohru Nakamura ,  Nakazato Kazuo ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/76229 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/732

摘要： A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps the carriers given by the emitter from getting trapped inside, thereby preventing the cut-off frequency from dropping.

摘要翻译： 发射极和隔离区域之间的距离保持在由发射极深度和基底宽度（即，基底在深度方向上的厚度）确定的范围内的垂直双极晶体管布置。 这样可以防止发射器的载波被捕获到内部，从而防止截止频率的下降。

公开(公告)号：US4949151A

公开(公告)日：1990-08-14

申请号：US100232

申请日：1987-09-23

申请人： Masatada Horiuchi ,  Katsuyoshi Washio ,  Tohru Nakamura

发明人： Masatada Horiuchi ,  Katsuyoshi Washio ,  Tohru Nakamura

IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L23/485 ,  H01L27/082 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

CPC分类号： H01L29/66272 ,  H01L21/743 ,  H01L23/485 ,  H01L27/0823 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/456 ,  H01L2924/0002

摘要： A high integration bipolar transistor operable at very high operating speed is disclosed. A semiconductor device of this invention has a semiconductor substrate of a first conductivity type, a buried impurity region formed on the substrate, and a bipolar transistor formed on the buried impurity region, wherein a plurality of monocrystalline active regions defined by the buried impurity region are isolated from each other by an element isolation insulator, the buried impurity region is connected to a graft region formed on the element isolation insulator at least at the side wall of the buried impurity region, and connected to a semiconductor element in a different active region via the graft region.

摘要翻译： 公开了以非常高的工作速度工作的高集成度双极晶体管。 本发明的半导体器件具有第一导电类型的半导体衬底，形成在衬底上的掩埋杂质区域和形成在掩埋杂质区域上的双极晶体管，其中由掩埋杂质区域限定的多个单晶有源区域是 通过元件隔离绝缘体彼此隔离，所述掩埋杂质区至少在所述掩埋杂质区的侧壁处连接到形成在所述元件隔离绝缘体上的移植区域，并且经由所述掩模杂质区域连接到不同有源区域中的半导体元件 移植区域。

公开(公告)号：US5523602A

公开(公告)日：1996-06-04

申请号：US291652

申请日：1994-08-16

申请人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

发明人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/304 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/1203

摘要： Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate. The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

摘要翻译： 公开了一种多层SOI衬底，其包括支撑衬底和层叠在支撑衬底的主表面上的第一绝缘体，半导体膜，第二绝缘体和单晶半导体膜（SOI膜）。 SOI衬底通过直接接合技术形成，并且使用单晶半导体膜（SOI层）形成双极晶体管和MOS晶体管。 可以在没有外延生长的情况下形成极浅的结，从而以低成本显着提高半导体器件的操作速度。

公开(公告)号：US5109263A

公开(公告)日：1992-04-28

申请号：US556365

申请日：1990-07-24

申请人： Mitsuo Nanba ,  Tohru Nakamura ,  Kazuo Nakazato ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

发明人： Mitsuo Nanba ,  Tohru Nakamura ,  Kazuo Nakazato ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

IPC分类号： H01L21/331 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/76229 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/732

摘要： A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps the carriers given by the emitter from getting trapped inside, thereby preventing the cut-off frequency from dropping.

摘要翻译： 发射极和隔离区域之间的距离保持在由发射极深度和基底宽度（即，基底在深度方向上的厚度）确定的范围内的垂直双极晶体管布置。 这样可以防止发射器的载波被捕获到内部，从而防止截止频率的下降。

公开(公告)号：US5424575A

公开(公告)日：1995-06-13

申请号：US890787

申请日：1992-06-01

申请人： Katsuyoshi Washio ,  Tohru Nakamura ,  Takahiro Onai ,  Masatada Horiuchi ,  Takashi Uchino

发明人： Katsuyoshi Washio ,  Tohru Nakamura ,  Takahiro Onai ,  Masatada Horiuchi ,  Takashi Uchino

IPC分类号： H01L21/331 ,  H01L27/12 ,  H01L29/06 ,  H01L29/73 ,  H01L29/72

CPC分类号： H01L29/7317 ,  H01L27/1203 ,  H01L29/0692

摘要： A semiconductor device has an electrically insulating substrate and a semiconductor layer formed on the insulating substrate. A plurality of semiconductor regions are defined so as to be joined to each other to form at least two homojunctions in the semiconductor layer. A lead conductor for one of the semiconductor regions which is required to have a small thickness has a specific structure such that the lead conductor is in contact with the one semiconductor region at the main surface of the semiconductor layer for electrical connection therebetween and extends over that portion of the semiconductor layer which contributes to definition of at least one of the semiconductor regions other than the first-mentioned one semiconductor region.

摘要翻译： 半导体器件具有形成在绝缘基板上的电绝缘基板和半导体层。 多个半导体区域被定义为彼此接合以在半导体层中形成至少两个同态。 需要具有小厚度的半导体区域之一的引线导体具有特定结构，使得引线导体与半导体层的主表面处的一个半导体区域接触，以在其间进行电连接，并延伸超过该半导体区域 部分半导体层有助于定义除了前述一个半导体区域以外的半导体区域中的至少一个。

公开(公告)号：US4887145A

公开(公告)日：1989-12-12

申请号：US937610

申请日：1986-12-03

申请人： Katsuyoshi Washio ,  Tohru Nakamura ,  Kazuo Nakazato ,  Masatada Horiuchi ,  Tetsuya Hayashida

发明人： Katsuyoshi Washio ,  Tohru Nakamura ,  Kazuo Nakazato ,  Masatada Horiuchi ,  Tetsuya Hayashida

IPC分类号： H01L21/285 ,  H01L21/32 ,  H01L21/331 ,  H01L29/423 ,  H01L29/732 ,  H01L29/04

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/32 ,  H01L29/42304 ,  H01L29/7325

摘要： A bipolar transistor capable of operating at high speeds. In a bipolar transistor designed for operation at high speeds, a polycrystalline silicon layer used as a base electrode effects is a contact area with respect to the base region which lacks precision or tends to increase. Further, when the transistor is formed in a small size, the ratio of the contact area with respect to the polycrystalline area increases, making it difficult to increase the operation speed. In order to reduce the contact area of the polycrystalline silicon layer, this invention deals with the structure in which the polycrystalline silicon layer is brought into contact with a portion near the edge of the convex semiconductor layer maintaining a small size and a high precision.

摘要翻译： 能够高速运行的双极晶体管。 在设计用于高速运行的双极晶体管中，用作基极效应的多晶硅层是相对于缺少精度或倾向于增加的基极区域的接触面积。 此外，当晶体管形成为小尺寸时，接触面积相对于多晶面积的比率增加，使得难以提高操作速度。 为了减少多晶硅层的接触面积，本发明涉及多晶硅层与凸半导体层的边缘附近的部分接触的结构，保持小尺寸和高精度。

公开(公告)号：US07098740B2

公开(公告)日：2006-08-29

申请号：US10688976

申请日：2003-10-21

申请人： Masao Kondo ,  Toru Masuda ,  Katsuyoshi Washio

发明人： Masao Kondo ,  Toru Masuda ,  Katsuyoshi Washio

IPC分类号： H03F3/68

CPC分类号： H03F3/211 ,  H03F1/302 ,  H03F2200/372 ,  H03F2203/21178

摘要： There is provided not only a radio frequency power amplifier using an SiGe HBT subject to a little amplification distortion, but also a communication system using the same. A conventional radio frequency power amplifier provides base bias paths of transistors Q1 through QN (SiGe HBT) with bias resistors R11 through R1N having resistance values three to five times higher than those of a ballast resistor attached to each transistor's base. A coil LB is provided in parallel with the bias resistor as a means for compensating a voltage drop due to direct current component IDC flowing through the bias resistor. Addition of the bias resistor suppresses non-linearity of low-frequency variations in an output current. Addition of the coil compensates for voltage drop. Accordingly, the maximum linear output power can be improved. As a result, it is possible to provide the power amplifier subject to a little amplification distortion within a wide output range.

摘要翻译： 不仅提供使用SiGe HBT的射频功率放大器，而且具有很小的放大失真，而且还提供了使用它的通信系统。 传统的射频功率放大器提供具有偏置电阻器R11至R11的晶体管Q 1至Q N（SiGe HBT）的基极偏置路径， SUB> 1N 的电阻值是连接到每个晶体管基极的镇流电阻的三到五倍。 作为用于补偿流过偏置电阻器的直流分量I DC的电压降的装置，设置有与偏压电阻并联的线圈L B B。 增加偏置电阻抑制输出电流中低频变化的非线性。 线圈的添加补偿电压降。 因此，可以提高最大线性输出功率。 结果，可以在宽的输出范围内提供具有小的放大失真的功率放大器。