公开(公告)号：US5629882A

公开(公告)日：1997-05-13

申请号：US115756

申请日：1993-09-03

申请人： Eiji Iwata

发明人： Eiji Iwata

IPC分类号： G06F17/14 ,  G06F7/38

CPC分类号： G06F17/147 ,  G06F17/145

摘要： An 8.times.8 discrete cosine transformation (8.times.8 DCT) system with minimum multiplications, without a reduced accuracy of calculation, and operable at a high speed, and an 8.times.8 inverse discrete cosine transformation (IDCT) system are disclosed. The transformation matrices for an 8.times.8 DCT are factorized into a constant matrix [Q] and a matrix [R], and the relationship between the original input data [X] and the output matrix data [C] can be defined by [C]=1/2.multidot.[R] [Q] [X]. The matrix [Q] consists of 0, 1, and -1, while the matrix [R] consists of irrational numbers defined by the 8.times.8 DCT. The computation of the constant matrix [Q] to the matrix data [X] can be realized by an addition and subtraction operation, while multiplication is performed just for the computation of the matrix [R]. The addition and subtraction circuit performs a computation between [X] and [Q], while the multiplication and addition circuit performs a computation between the result of computation of the addition and subtraction circuit and the matrix [R]. Also, an 8.times.8 IDCT performs the computation inverse to the 8.times.8 DCT.

摘要翻译： 公开了一种具有最小乘法的8×8离散余弦变换（8×8 DCT）系统，没有降低的计算精度并且可以高速运行，并且具有8×8的逆离散余弦变换（IDCT）系统。 8×8 DCT的变换矩阵被分解为常数矩阵[Q]和矩阵[R]，原始输入数据[X]和输出矩阵数据[C]之间的关系可以由[C] = + E，fra 1/2 + EE x [R] [Q] [X]。 矩阵[Q]由0，1和-1组成，而矩阵[R]由8x8 DCT定义的无理数组成。 常数矩阵[Q]到矩阵数据[X]的计算可以通过加法运算和减法运算来实现，而乘法仅用于矩阵[R]的计算。 加法和减法电路在[X]和[Q]之间执行计算，而乘法和加法电路执行加法和减法电路的计算结果与矩阵[R]之间的计算。 此外，8×8 IDCT执行与8×8 DCT相反的计算。

公开(公告)号：US20120047355A1

公开(公告)日：2012-02-23

申请号：US13189809

申请日：2011-07-25

申请人： Eiji Iwata ,  Ryohei Okada

发明人： Eiji Iwata ,  Ryohei Okada

IPC分类号： G06F9/305

CPC分类号： H03M7/40

摘要： An information processing apparatus operates data stored in an input register for each bit and stores a result thereof in an output register. A selector circuit selects output data of a bit from input data of 128 bits in the input register. An AND circuit outputs, only when data from a corresponding selector circuit is valid, the data to a corresponding bit of the output register. A control signal generator inputs a select signal indicating the number of a bit to be selected to each selector circuit, and also inputs a signal indicating whether data input from the selector circuit is valid or invalid to each AND circuit.

摘要翻译： 信息处理装置对每个位操作存储在输入寄存器中的数据，并将其结果存储在输出寄存器中。 选择器电路从输入寄存器中的128位的输入数据中选择位的输出数据。 只有当来自相应的选择器电路的数据有效时，AND电路才输出数据到输出寄存器的相应位。 控制信号发生器向每个选择器电路输入指示要选择的位的数目的选择信号，并且还输入指示从选择器电路输入的数据对每个“与”电路是有效还是无效的信号。

公开(公告)号：US20060101246A1

公开(公告)日：2006-05-11

申请号：US10959613

申请日：2004-10-06

申请人： Eiji Iwata

发明人： Eiji Iwata

IPC分类号： G06F9/44

CPC分类号： G06F9/30018 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/3824

摘要： A bit manipulation processor, system and method are provided which reduces the number of operations performed during data processing. An additional register is used as a buffer. The buffer has a bit length which is preferably greater than the address boundaries in a memory or register address. A bitstream can be processed using the buffer by itself or in combination with a standard register, depending upon the particular function to be implemented.

摘要翻译： 提供了一种位操作处理器，系统和方法，其减少了数据处理期间执行的操作次数。 一个附加寄存器用作缓冲区。 缓冲器的位长度优选地大于存储器或寄存器地址中的地址边界。 根据要实现的特定功能，可以使用缓冲器本身或与标准寄存器组合来处理比特流。

公开(公告)号：US20060069879A1

公开(公告)日：2006-03-30

申请号：US11236262

申请日：2005-09-27

申请人： Keisuke Inoue ,  Eiji Iwata

发明人： Keisuke Inoue ,  Eiji Iwata

IPC分类号： G06F13/28 ,  G06F15/167

CPC分类号： G06F13/28 ,  G06F15/167

摘要： The present invention provides methods and apparatus for transferring and storing data among processors and memory in a multiprocessor system. The data is compressed locally before it is sent to a shared memory. The memory stores the data in its compressed state, but the data is aligned in the memory in the same manner as uncompressed data would be. A tag table keeps track of the compression type and compressed data size for a set of data at a given address block. A data compressor and a data expander may be implemented in a direct memory access controller accessible to multiple coprocessors, or the compressor and the expander may be implemented within the coprocessors.

摘要翻译： 本发明提供了用于在多处理器系统中在处理器和存储器之间传送和存储数据的方法和装置。 在将数据发送到共享内存之前，将数据压缩到本地。 存储器将数据存储在其压缩状态，但数据以与未压缩数据相同的方式存储在存储器中。 标签表跟踪给定地址块上的一组数据的压缩类型和压缩数据大小。 可以在可由多个协处理器访问的直接存储器访问控制器中实现数据压缩器和数据扩展器，或者压缩器和扩展器可以在协处理器内实现。

公开(公告)号：US06870883B2

公开(公告)日：2005-03-22

申请号：US09352422

申请日：1999-07-12

申请人： Eiji Iwata

发明人： Eiji Iwata

IPC分类号： H04N19/50 ,  G06F9/50 ,  G06T1/20 ,  G06T9/00 ,  H03M7/40 ,  H04N1/41 ,  H04N19/423 ,  H04N19/436 ,  H04N19/503 ,  H04N19/51 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/91 ,  H04B1/66

CPC分类号： H04N19/436 ,  H04N19/42 ,  H04N19/61 ,  H04N19/91

摘要： Encoding and decoding systems for MPEG encoding and decoding at a high speed using a parallel processing system, wherein macroblocks to be processed are designated for first to third processors which are made to carry out all processings of encoding, variable length coding, and local decoding of those macroblocks; the variable length coding is carried out after confirming that the variable length coding with respect to the previous macroblock is ended; the variable length coding which was normally sequentially carried out at a specific processor is carried out at all of the processors; and the encoding and local decoding are carried out at all of the processors; whereby the loads are dispersed, the efficiency is improved as a whole, and the processing speed becomes fast.

摘要翻译： 用于使用并行处理系统以高速进行MPEG编码和解码的编码和解码系统，其中要处理的宏块被指定用于第一至第三处理器，用于执行编码，可变长度编码和本地解码的所有处理 那些宏块 在确认相对于前一个宏块的可变长度编码结束之后执行可变长度编码; 在所有处理器中执行通常在特定处理器处顺序执行的可变长度编码; 并且在所有处理器上执行编码和本地解码; 由此负载分散，整体上提高效率，加工速度变快。

公开(公告)号：US5654910A

公开(公告)日：1997-08-05

申请号：US101750

申请日：1993-08-04

申请人： Eiji Iwata

发明人： Eiji Iwata

IPC分类号： G06F17/14

CPC分类号： G06F17/147

摘要： A two-dimensional 4.times.4 discrete cosine transformation (4.times.4 DCT) in which the number of multiplications is small and the calculation precision is not lowered can be defined by the relationship between input matrix data [X] and output matrix data [Y], by [Y]=1/4.multidot.[W] [V] [R] [Q] [R] [Q] [X] as factorization equations. The matrices [R], [Q], and [V] are constant matrices including "0", "1", and "-1", and the matrix [W] is a matrix indicating irrational numbers defined by two-dimensional 4.times.4 DCT. The computation of the constant matrices [R], [Q], and [V] can be realized by addition-subtraction, and the multiplication is carried out only for the computation of matrix [W]. The first addition-subtraction circuit (2) performs the first computation between [X] and [RQ] and the first computation between this result with [RQ] by time division, the second addition-subtraction circuit (2) performs the remaining second computation between [RQ] and [S] and a third computation between this result and [V] by time division, and the multiplication-addition circuit (6) performs the computation between [U] and [W]. The intermediate value holding circuits (3 and 5) hold the intermediate calculation values in the time division computation.

摘要翻译： 可以通过输入矩阵数据[X]和输出矩阵数据[Y]之间的关系来定义乘法数量小并且计算精度不降低的二维4×4离散余弦变换（4×4 DCT） Y] = + E，fra 1/4 + EE x [W] [V] [R] [Q] [R] [Q] [X] 矩阵[R]，[Q]和[V]是包括“0”，“1”和“-1”的常数矩阵，矩阵[W]是表示由二维4×4 DCT。 可以通过加减法来实现常数矩阵[R]，[Q]和[V]的计算，并且仅对矩阵[W]的计算执行乘法。 第一加减法电路（2）通过时分执行[X]和[RQ]之间的第一次计算和该结果与[RQ]之间的第一次计算，第二加减法电路（2）执行剩余的第二计算 在[RQ]和[S]之间，并且通过时间分割在该结果与[V]之间进行第三次计算，并且乘法相加电路（6）执行[U]和[W]之间的计算。 中间值保持电路（3和5）在时分计算中保持中间计算值。

公开(公告)号：US5604546A

公开(公告)日：1997-02-18

申请号：US324713

申请日：1994-10-18

申请人： Eiji Iwata

发明人： Eiji Iwata

IPC分类号： G06T1/20 ,  G06T7/20 ,  G06T7/60 ,  H04N5/14 ,  H04N19/00 ,  H04N19/423 ,  H04N19/436 ,  H04N19/46 ,  H04N19/503 ,  H04N19/51 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/85 ,  H04N19/91 ,  H04N7/30 ,  H04N7/32

CPC分类号： G06T7/202 ,  H04N19/186 ,  H04N19/51 ,  H04N19/577 ,  H04N5/145 ,  G06T2207/10016

摘要： An image data processing circuit for detection of a motion vector by dividing one frame unit of an image signal into a plurality of blocks, each consisting of a predetermined number of pixel data, and performing a search over all frames of the image signal by a block-matching method, as a block size of a reference block of a current frame of the image signal M.times.N pixels, the number of candidate blocks of the previous frame of the image signal being M.times.N. The processing circuit performs processing for detection of motion vectors able to simultaneously obtain three types of motion vectors: the motion vector at the even number field, the motion vector at the odd number field, and the motion vector at the frame.

摘要翻译： 一种图像数据处理电路，用于通过将图像信号的一帧单位划分成多个块，每个块由预定数量的像素数据组成，并通过块执行对图像信号的所有帧的搜索来检测运动矢量 作为图像信号M×N个像素的当前帧的参考块的块大小，图像信号的前一帧的候选块的数量为M×N。 处理电路执行用于检测能够同时获得三种类型的运动矢量的运动矢量的处理：偶数场的运动矢量，奇数场的运动矢量和帧处的运动矢量。

公开(公告)号：US4790237A

公开(公告)日：1988-12-13

申请号：US835227

申请日：1986-03-03

申请人： Masashi Usuda ,  Kiyoshi Shimizu ,  Eiji Iwata ,  Hideo Yamada ,  Kazutaka Onozuka ,  Toshio Kuno ,  Hideo Kuno ,  Yukio Kuno

发明人： Masashi Usuda ,  Kiyoshi Shimizu ,  Eiji Iwata ,  Hideo Yamada ,  Kazutaka Onozuka ,  Toshio Kuno ,  Hideo Kuno ,  Yukio Kuno

IPC分类号： F24F7/02 ,  F24F13/10

CPC分类号： F24F13/10 ,  F24F7/02 ,  Y10T137/87772

摘要： A damper for use in controlling the flow rate or direction of a flow of air or fumes flowing out from a room or space or flowing through a ventilation system, including a housing having at least one inlet opening. The housing has a tubular side wall in which are provided a plurality of outlet apertures opened and closed by associated closure members which are adapted to swing to and away from the side wall, preferable inwardly of the housing. The total flow area of the outlet apertures may be extended to a desired degree by increasing the axial length and diameter of the side wall of the housing, whereby the flow resistance and pressure drop across the damper are reduced.

摘要翻译： 用于控制从房间或空间流出或流过通风系统的空气或烟雾流动的流量或方向的阻尼器，包括具有至少一个入口的壳体。 壳体具有管状侧壁，其中设置有多个出口孔，该多个出口孔由关闭的闭合构件打开和关闭，该闭合构件适于摆动到或远离侧壁，优选地在壳体的内部。 通过增加壳体的侧壁的轴向长度和直径，出口孔的总流动面积可以延伸到期望的程度，从而降低阻尼器上的流动阻力和压降。