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109 条记录 (耗时 0.03 秒)

    Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device
    22.
    发明授权
    Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device 失效
    在制造半导体器件期间缝合由相邻图像图案定义的片段的方法

    公开(公告)号：US6030752A

    公开(公告)日：2000-02-29

    申请号：US805534

    申请日：1997-02-25

    申请人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

    发明人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

    IPC分类号： G03F7/20

    CPC分类号： G03F7/70475

    摘要： A method of stitching segments defined by adjacent image patterns of a photolithographic system during the manufacture of a semiconductor device is disclosed. The method includes forming a material over a semiconductor substrate, projecting a first image pattern over the substrate that defines a first segment and a contact region, projecting a second image pattern over the substrate that defines a second segment with an end that overlaps the contact region, and removing a portion of the material corresponding to the first and second image patterns to form the first and second segments stitched by a portion of the contact region. The contact region has a greater width than the first and second segments. In this manner, the contact region accommodates misalignments that might otherwise lead to inadequate coupling or decoupling between the first and second segments. The invention is particularly well-suited for stitching polysilicon gates of N-channel and P-channel devices.

    摘要翻译： 公开了一种在制造半导体器件期间缝合由光刻系统的相邻图像图案限定的片段的方法。 该方法包括在半导体衬底上形成材料，将限定第一部分和接触区域的第一图案图案投影在衬底上，将限定第二部分的第二图像图案投影在衬底上，端部与接触区域重叠 以及去除对应于第一和第二图像图案的材料的一部分以形成由接触区域的一部分缝合的第一和第二段。 接触区域具有比第一和第二段更大的宽度。 以这种方式，接触区域适应可能导致第一和第二段之间不充分的耦合或解耦的未对准。 本发明特别适用于拼接N沟道和P沟道器件的多晶硅栅极。

    Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device
    23.
    发明授权
    Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device 失效
    在器件中栅极形成之前使用瞬态增强扩散来控制掺杂剂浓度的方法

    公开(公告)号：US5976956A

    公开(公告)日：1999-11-02

    申请号：US837936

    申请日：1997-04-11

    申请人： Mark I. Gardner ,  Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore

    发明人： Mark I. Gardner ,  Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore

    IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/322 ,  H01L29/78

    CPC分类号： H01L21/26506 ,  H01L21/3221 ,  Y10S148/024 ,  Y10S148/06

    摘要： Dopant atoms have coefficients of diffusion that vary due to implant damage. Damaged regions are selected and created by implanting silicon atoms into a silicon substrate prior to formation of a gate electrode. The silicon atoms act as a getter for attracting selected dopants that are trapped in the silicon substrate. Dopants are implanted in the vicinity of the damaged regions and diffused by transient-enhanced diffusion (TED) into the damaged regions by thermal cycling to accumulate dopant atoms. Transient-enhanced diffusion improves the doping of a substrate by enhancing the diffusion of dopants at relatively low anneal temperatures. Dopant accumulation sets particular selected electrical properties without placing an excessive amount of dopant in regions adjacent to junctions for purposes including threshold control for a field device, threshold setting for a transistor, and prevention of device punchthrough.

    摘要翻译： 掺杂原子具有由于植入物损伤而变化的扩散系数。 通过在形成栅电极之前将硅原子注入到硅衬底中来选择并产生损伤区域。 硅原子用作吸收被捕获在硅衬底中的所选掺杂剂的吸气剂。 掺杂剂被注入到受损区域附近，并通过热循环通过瞬态增强扩散（TED）扩散到受损区域以积累掺杂剂原子。 瞬态增强扩散通过在相对低的退火温度下增强掺杂剂的扩散来改善衬底的掺杂。 掺杂剂累积设置特定选择的电性能，而不会在邻近接点的区域中放置过量的掺杂剂，包括用于现场设备的阈值控制，晶体管的阈值设置以及防止器件穿透。

    Dissolvable dielectric method
    24.
    发明授权
    Dissolvable dielectric method 失效
    溶解介电法

    公开(公告)号：US5953626A

    公开(公告)日：1999-09-14

    申请号：US659166

    申请日：1996-06-05

    申请人： Fred N. Hause ,  Basab Bandyopadhyay ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  William S. Brennan

    发明人： Fred N. Hause ,  Basab Bandyopadhyay ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  William S. Brennan

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/7682

    摘要： A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact. In one embodiment of the invention, a passivation layer is formed on the second interconnect level prior to dissolving the temporary material. The air gap dielectric can be used with more than two levels of interconnect, if desired.

    摘要翻译： 一种制造气隙电介质的制造工艺，其中在临时支撑材料上形成多层互连结构。 随后将临时材料溶解掉，留下由空气组成的层间和层间电介质。 在本发明的一个实施例中，在阻挡层上形成第一互连电平。 然后在第一互连层上形成临时支撑材料，并在临时支撑材料上形成第二层互连。 在形成第二互连级别之前，在临时材料中形成多个柱状开口并填充有导电材料。 除了在第一和第二级互连之间提供接触之外，支柱为第二互连电平提供机械支撑。 临时材料溶解在攻击临时材料的溶液中，但使互连材料和支柱材料完好无损。 在本发明的一个实施例中，在溶解临时材料之前，在第二互连层上形成钝化层。 如果需要，气隙电介质可以与多于两个级别的互连一起使用。

    Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device
    26.
    发明授权
    Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device 失效
    通过多晶硅栅极注入硅的方法，用于半导体器件的穿通控制

    公开(公告)号：US5899732A

    公开(公告)日：1999-05-04

    申请号：US837937

    申请日：1997-04-11

    申请人： Mark I. Gardner ,  Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore

    发明人： Mark I. Gardner ,  Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore

    IPC分类号： H01L21/225 ,  H01L21/265 ,  H01L21/322 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10

    CPC分类号： H01L29/66492 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/3221 ,  H01L21/8238 ,  H01L29/1083 ,  H01L29/6659

    摘要： A region of damaged silicon is exploited as a gettering region for gettering impurities in a silicon substrate. The region of damaged silicon is formed between source and drain regions of a device by implanting silicon atoms into the silicon substrate after the formation of a gate electrode of the device. The damaged region is subsequently annealed and, during the annealing process, dopant atoms such as boron segregate to the region, locally increasing the dopant concentration in the region. The previously damaged region is in a location that determine the punchthrough characteristics of the device. The silicon implant for creating a gettering effect is performed after gate formation so that the region immediately beneath the junction is maintained at a lower dopant concentration to reduce junction capacitance. Silicon is implanted in the vicinity of a polysilicon gate to induce transient-enhanced diffusion (TED) of dopant atoms such as boron or phosphorus for control of punchthrough characteristics of a device. A punchthrough control implant is performed following formation of gate electrodes on a substrate using a self-aligned gettering implant.

    摘要翻译： 受损硅的区域被用作吸杂硅衬底中的杂质的吸杂区域。 损坏的硅的区域在器件的栅极电极形成之后通过将硅原子注入到硅衬底中而在器件的源极和漏极区域之间形成。 受损区域随后退火，并且在退火过程期间，诸如硼的掺杂剂原子偏析到该区域，局部地增加该区域中的掺杂剂浓度。 先前损坏的区域位于确定设备穿透特性的位置。 用于产生吸杂效应的硅植入物在栅极形成之后进行，使得紧邻在结点处的区域保持在较低掺杂剂浓度以减小结电容。 将硅注入到多晶硅栅极附近以引发诸如硼或磷的掺杂剂原子的瞬态增强扩散（TED），以控制器件的穿透特性。 在使用自对准吸气植入物在衬底上形成栅电极之后执行穿通控制植入。

    Reticle that compensates for radiation-induced lens error in a photolithographic system
    27.
    发明授权
    Reticle that compensates for radiation-induced lens error in a photolithographic system 失效
    补偿光刻系统中辐射诱发的透镜误差的光罩

    公开(公告)号：US5888675A

    公开(公告)日：1999-03-30

    申请号：US760031

    申请日：1996-12-04

    申请人： Bradley T. Moore ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Derick J. Wristers

    发明人： Bradley T. Moore ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Derick J. Wristers

    IPC分类号： G03F1/00 ,  G03F7/20 ,  H01L21/027 ,  G03F9/00 ,  G03C5/00

    CPC分类号： G03F7/70433 ,  G03F1/70 ,  G03F7/70241

    摘要： A reticle provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions, for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.

    摘要翻译： 掩模版提供图像图案并补偿光刻系统中的透镜误差。 使用指示透镜误差的图像位移数据对结构上的掩模版进行修改。 可以通过调节辐射透射区域的构造（或布局）来结构地修改掩模版，例如通过调节石英基底的顶表面上的铬图案。 或者，可以通过调整掩模版的曲率来结构地修改掩模版，例如通过在石英基底的顶表面上提供铬图案并研磨掉石英基底的底表面的部分。 图像位移数据也可以根据透镜加热而变化，使得掩模版补偿与标线图案相关联的透镜加热。

    Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric
    28.
    发明授权
    Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric 失效
    复合栅电极，其与掺杂剂扩散阻滞层结合，邻近底层栅极电介质

    公开(公告)号：US5885877A

    公开(公告)日：1999-03-23

    申请号：US837581

    申请日：1997-04-21

    申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Daniel Kadosh ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

    发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Daniel Kadosh ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

    IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/336 ,  H01L21/3205

    CPC分类号： H01L21/28035 ,  H01L29/4916

    摘要： A composite gate electrode layer incorporates a diffusion-retarding barrier layer disposed at the bottom of the gate electrode layer to reduce the amount of dopant which diffuses into the gate dielectric layer from the gate electrode layer. A lower nitrogen-containing gate electrode layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate dielectric layer disposed therebelow, and an upper gate electrode layer is formed upon the lower layer and is doped to form a highly conductive layer. Together the first and second gate electrode layers form a composite gate electrode layer which incorporates a diffusion-retarding barrier layer adjacent to the underlying gate dielectric layer. The barrier layer may be formed by annealing a first polysilicon layer in a nitrogen-containing ambient, such as N.sub.2, NO, N.sub.2 O, and NH.sub.3, by implanting a nitrogen-containing material, such as elemental or molecular nitrogen, into a first polysilicon layer, and by in-situ depositing a nitrogen-doped first polysilicon layer. Diffusion of dopants into the gate dielectric layer may be retarded, as most dopant atoms are prevented from diffusing from the composite gate electrode layer at all. In addition, the nitrogen concentration within the gate dielectric layer, particularly at or near the substrate interface, may be maintained at lower concentrations than otherwise necessary to prevent dopant diffusion into the underlying substrate. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness less than approximately 60 .ANG. when using a p-type dopant, such as boron.

    摘要翻译： 复合栅极电极层包括设置在栅极电极层底部的扩散阻挡层，以减少从栅极电极层扩散到栅极电介质层中的掺杂剂的量。 下部含氮栅电极层提供阻止扩散阻挡层，以阻止掺杂剂扩散到设置在其下方的栅介质层中，并且在下层上形成上栅极电极层，并且被掺杂以形成高导电层。 第一和第二栅极电极层一起形成复合栅极电极层，该复合栅极电极层包含与下面的栅极电介质层相邻的扩散阻滞阻挡层。 通过将含氮材料（例如元素或分子氮）注入到第一多晶硅层中，可以通过在氮气环境如N 2，NO，N 2 O和NH 3中退火第一多晶硅层来形成阻挡层 ，并通过原位沉积氮掺杂的第一多晶硅层。 完全可以防止掺杂剂扩散到栅极电介质层中，因为大多数掺杂剂原子被阻止从复合栅极电极层扩散。 此外，栅极电介质层内，特别是在衬底界面处或附近的氮浓度可以保持在比防止掺杂剂扩散到下面的衬底中所必需的更低的浓度。 本发明特别适用于薄栅电介质，例如当使用诸如硼的p型掺杂剂时厚度小于约60的薄电介质。

    Method of reducing overlap between gate electrode and LDD region
    29.
    发明授权
    Method of reducing overlap between gate electrode and LDD region 失效
    减少栅电极与LDD区重叠的方法

    公开(公告)号：US5869378A

    公开(公告)日：1999-02-09

    申请号：US637980

    申请日：1996-04-26

    申请人： Mark W. Michael

    发明人： Mark W. Michael

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/6659 ,  H01L21/28123 ,  H01L29/7833

    摘要： A method of manufacturing an integrated circuit so as to reduce overlap between an LDD region and a gate electrode is disclosed. The method includes forming a gate electrode on a gate insulator on a semiconductor substrate, implanting a lightly-doped drain (LDD) region in the substrate using the gate electrode as a mask, removing a lateral portion of the gate electrode after implanting the LDD region, and then laterally diffusing the LDD region into the substrate such that a lateral edge of the LDD region is substantially aligned with a lateral edge of the gate electrode. Preferably, the lateral portion of the gate electrode is removed using an isotropic etch. The method further includes forming a spacer adjacent to an edge of the gate electrode after removing the lateral portion, and then implanting a heavily-doped region using the spacer and gate electrode as an implant mask.

    摘要翻译： 公开了一种制造集成电路以减少LDD区和栅电极之间的重叠的方法。 该方法包括在半导体衬底上的栅极绝缘体上形成栅电极，使用栅电极作为掩模将轻掺杂漏极（LDD）区域注入到衬底中，在注入LDD区之后去除栅电极的侧向部分 ，然后将LDD区域横向扩散到衬底中，使得LDD区域的横向边缘基本上与栅电极的侧边缘对齐。 优选地，使用各向同性蚀刻去除栅电极的侧向部分。 该方法还包括在去除侧面部分之后形成邻近栅电极的边缘的间隔物，然后使用间隔物和栅极电极注入重掺杂区域作为植入物掩模。