公开(公告)号：US20060176885A1

公开(公告)日：2006-08-10

申请号：US11054910

申请日：2005-02-10

申请人： Benjiman Goodman ,  Praveen Reddy ,  Jeffrey Stuecheli

发明人： Benjiman Goodman ,  Praveen Reddy ,  Jeffrey Stuecheli

IPC分类号： H04L12/28

CPC分类号： G06F12/0831 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0851

摘要： A data processing system includes an interconnect fabric, a protected resource having a plurality of banks each associated with a respective one of a plurality of address sets, a snooper that controls access to the resource, one or more masters that initiate requests, and interconnect logic coupled to the one or more masters and to the interconnect fabric. The interconnect logic regulates a rate of delivery to the snooper via the interconnect fabric of requests that target any one the plurality of banks of the protected resource.

摘要翻译： 数据处理系统包括互连结构，受保护资源具有多个存储体，每个存储体各自与多个地址集合中的相应一个地址集相关联，控制对资源的访问的监听器，发起请求的一个或多个主站和互连逻辑 耦合到一个或多个主器件和互连结构。 互连逻辑通过针对受保护资源的多个组中的任一个的请求的互连结构来调节到窥探者的传送速率。

公开(公告)号：US20070226427A1

公开(公告)日：2007-09-27

申请号：US11388017

申请日：2006-03-23

申请人： Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

发明人： Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F2212/507

摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping an exclusive access operation, the exclusive access request specifying a target address matching the address tag and indicating a relative domain location of a requester that initiated the exclusive access operation, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and whether a target memory block associated with the address tag is cached within the first coherency domain upon successful completion of the exclusive access operation based upon the relative location of the requestor.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 在数据处理系统的第一相关域内的第一高速缓冲存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态， 存储位置不包含有效数据。 响应于窥探独占访问操作，专用访问请求指定与地址标签匹配的目标地址，并且指示发起独占访问操作的请求者的相对域位置，第一高速缓存存储器从第一数据更新相关性状态字段 - 无效的一致性状态到指示地址标签有效的第二数据无效一致性状态，存储位置不包含有效数据，以及与地址标签相关联的目标存储器块是否被缓存在第一相关域内 基于请求者的相对位置成功完成独占访问操作。

公开(公告)号：US20070168639A1

公开(公告)日：2007-07-19

申请号：US11333607

申请日：2006-01-17

申请人： John McCalpin ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

发明人： John McCalpin ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0833 ,  G06F12/10 ,  G06F2212/507

摘要： A data processing system includes at least first and second coherency domains coupled by an interconnect fabric. A memory coupled to the interconnect fabric includes an address translation table having a translation table entry utilized to translate virtual memory addresses to real memory addresses. The translation table entry also includes scope information for broadcast operations targeting addresses within a memory region associated with the translation table entry. Scope prediction logic within the first coherency domain predictively selects a scope of broadcast of an operation on an interconnect fabric of the data processing system by reference to the scope information within the address translation table entry.

摘要翻译： 数据处理系统至少包括由互连结构耦合的第一和第二相干域。 耦合到互连结构的存储器包括具有用于将虚拟存储器地址转换为实际存储器地址的转换表项的地址转换表。 转换表条目还包括针对与转换表条目相关联的存储器区域内的地址的广播操作的范围信息。 第一相干域内的范围预测逻辑通过参考地址转换表条目中的范围信息预测性地选择数据处理系统的互连结构上的操作的广播范围。

公开(公告)号：US20060224833A1

公开(公告)日：2006-10-05

申请号：US11095734

申请日：2005-03-31

申请人： Guy Guthrie ,  Aaron Sawdey ,  William Starke ,  Jeffrey Stuecheli

发明人： Guy Guthrie ,  Aaron Sawdey ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F12/0811 ,  G06F12/0815 ,  G06F12/0831

摘要： In response to a master receiving a memory access request indicating a target address, the master accesses a first cache directory of an upper level cache of a cache hierarchy. In response to the target address being associated in the first cache directory with an entry having a valid address tag and a first invalid coherency state, the master issues a request specifying the target address on an interconnect fabric without regard to a coherency state associated with the target address in a second cache directory of a lower level cache of the cache hierarchy. In response to the target address having a second invalid coherency state with respect to the first cache directory, the master issues a request specifying the target address on an interconnect fabric after determining a coherency state associated with the target address in the second cache directory of the lower level cache of the cache hierarchy.

公开(公告)号：US20060179234A1

公开(公告)日：2006-08-10

申请号：US11054390

申请日：2005-02-09

申请人： Robert Bell ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： Robert Bell ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F12/126 ,  G06F12/0897 ,  G06F12/123 ,  G06F12/128

摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.

摘要翻译： 一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。 保护位用作用于标识要保护的同余类的成员的位置的指针。 在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。 保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。 由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。 使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下否定对被保护成员的选择。

公开(公告)号：US20060179232A1

公开(公告)日：2006-08-10

申请号：US11054067

申请日：2005-02-09

申请人： Robert Bell ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： Robert Bell ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F12/0888 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/1032

摘要： A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.

摘要翻译： 用于在LRU受害者选择期间防止选择被删除（D）成员作为LRU受害者的方法和装置。 在针对特定同余类的每个缓存访问期间，从高速缓存目录中的信息识别已删除的高速缓存行。 删除的高速缓存行的位置在LRU受害者选择期间通过高速缓存架构流水线化。 信息被锁存，然后传递给MRU向量生成逻辑。 生成MRU向量并将其传递给MRU更新逻辑，MRU更新逻辑是将删除的成员作为MRU成员进行选择/标记。 使MRU操作仅影响以基于树的结构状态位布置的较低级LRU状态位，使得MRU操作仅在D状态下否定特定成员的选择，而不影响其他成员的LRU受害者选择。

公开(公告)号：US20060277370A1

公开(公告)日：2006-12-07

申请号：US11146443

申请日：2005-06-06

申请人： Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

发明人： Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： In an entry of a first cache memory within a first coherency domain of a data processing system including at least first and second coherency domains, a coherency state field is set to a first state that indicates that an associated address tag is valid, an associated storage location does not contain valid data, and a memory block identified by the address tag is likely cached outside the first coherency domain. In response to snooping a castout operation, the first cache memory determines if the castout operation hits in the entry and, if so, updates the coherency state field from the first state to a second state indicating that the associated address tag is invalid.

公开(公告)号：US20060179238A1

公开(公告)日：2006-08-10

申请号：US11054871

申请日：2005-02-10

申请人： John Griswell ,  Hung Le ,  Francis O'Connell ,  William Starke ,  Jeffrey Stuecheli ,  Albert Williams

发明人： John Griswell ,  Hung Le ,  Francis O'Connell ,  William Starke ,  Jeffrey Stuecheli ,  Albert Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0862 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/383 ,  G06F12/0811

摘要： In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.

摘要翻译： 在具有加载/存储单元和预取硬件的微处理器中，预取硬件包括预取队列，其包含指示分配的数据流的条目。 预取引擎接收与由加载/存储单元执行的存储指令相关联的地址。 预取引擎通过将队列中的条目与包含多个高速缓存块的地址的窗口进行比较来确定是否对与存储指令相对应的预取队列中的条目进行分配，其中地址窗口从接收到的地址导出。 预取引擎将预取队列中的条目与两个连续高速缓存块的窗口进行比较。 当预取队列中的任何条目都在地址窗口内时，预取引擎抑制新条目的分配。 当存储指令的数据地址等于地址窗口的边界区域中的地址时，预取引擎进一步抑制新条目的分配。

公开(公告)号：US20060179222A1

公开(公告)日：2006-08-10

申请号：US11054925

申请日：2005-02-10

申请人： Vicente Chung ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： Vicente Chung ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/0851 ,  Y02D10/13

摘要： A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses. The first data bus can be one of a plurality of data busses in a first data bus set, and the second data bus can be one of a plurality of data busses in a second data bus set. Two address busses (one for each data bus set) are used to receive successive address tags that identify which portions of the requested memory values are being received from each data bus set. For example, the requested memory values may be 32 bytes each, and the separate portions of the requested memory values are received over four successive cycles with an 8-byte portion of each value received each cycle. The cache lines are spread across different cache sectors of the cache memory, wherein the cache sectors have different output latencies, and the separate portions of a given requested memory value are loaded sequentially into the corresponding cache sectors based on their respective output latencies. Merge flow circuits responsive to the cache controller are used to receive the portions of a requested memory value and input those bytes into the cache sector.

摘要翻译： 一种高速缓冲存储器，其通过在连续时钟周期的第一时间间隔内从第一数据总线接收第一请求存储器值的分开的部分来将两个存储器值加载到两个高速缓存行中，并且从第二数据接收第二请求存储器值的分离部分 总线与第一时间跨度重叠的连续时钟周期的第二时间跨度。 在说明性实施例中，第一输入线用于加载第一高速缓存行的第一字节数组和第二高速缓存行的第一字节数组，第二输入行用于加载第一高速缓存的第二字节数组 线和第二高速缓存线的第二字节阵列，并且第一和第二存储器值的分离部分的传输在第一和第二数据总线之间交错。 第一数据总线可以是第一数据总线组中的多个数据总线之一，并且第二数据总线可以是第二数据总线组中的多个数据总线中的一个。 两个地址总线（每个数据总线集合一个）用于接收连续的地址标签，其识别从每个数据总线组接收到所请求的存储器值的哪些部分。 例如，所请求的存储器值可以是每个32个字节，并且所请求的存储器值的分开的部分在四个连续周期中被接收，每个周期接收每个值的8字节部分。 高速缓存行分布在高速缓冲存储器的不同高速缓存扇区上，其中高速缓存扇区具有不同的输出延迟，并且给定请求的存储器值的分离部分基于它们各自的输出延迟顺序地加载到相应的高速缓存扇区中。 响应于高速缓存控制器的合并流回路用于接收请求的存储器值的部分并将这些字节输入高速缓存扇区。

公开(公告)号：US20060179248A1

公开(公告)日：2006-08-10

申请号：US11055640

申请日：2005-02-10

申请人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

发明人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F11/1064 ,  G06F12/0831

摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.

摘要翻译： 高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。 系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。 系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。 响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。