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公开(公告)号：US4546430A
公开(公告)日：1985-10-08
申请号：US513051
申请日：1983-07-13
申请人： David J. Moore , Larry L. Byers , Duane G. Kurth , Donald T. Bordsen , John R. Honkomp , Bruce C. Todd , Robert M. Malek
发明人： David J. Moore , Larry L. Byers , Duane G. Kurth , Donald T. Bordsen , John R. Honkomp , Bruce C. Todd , Robert M. Malek
CPC分类号： G06F13/20 , G06F13/122
摘要： In a system wherein a central computer complex is connected through central control modules (CCM) and channel modules (CM) to the control units of peripheral subsystems, a first queue is maintained in a CCM for Start I/O Fast (SIOF) commands waiting to be accepted by the CMs connected thereto. After a CM accepts an SIOF command and passes it on to a control unit, the control unit may return to the CM a busy status which is then passed through to the CCM. The CCM maintains a control unit busy (CUB) queue and an entry is made therein when busy status is returned. When a control unit reports control unit end status to the CCM, the CUB queue is linked to the top of the SIOF so that the CMs may again be informed that the SIOF commands are available. The arrangement avoids two interruptions of the central computer complex to report first that the control unit is busy and then that the control unit is available.
摘要翻译： 在中央计算机复合体通过中央控制模块（CCM）和信道模块（CM）连接到外围子系统的控制单元的系统中，第一个队列保持在用于启动I / O快速（SIOF）命令等待的CCM中 被连接到其的CM接受。 在CM接收到SIOF命令并将其传递给控制单元之后，控制单元可以将CM返回到繁忙状态，然后将其传递给CCM。 当忙碌状态返回时，CCM维护一个控制单元忙（CUB）队列并进入其中。 当控制单元将控制单元的结束状态报告给CCM时，CUB队列被链接到SIOF的顶部，使得CM再次被通知SIOF命令可用。 该装置避免中央计算机复合体的两次中断，首先报告控制单元正忙，然后控制单元可用。
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公开(公告)号：US5664089A
公开(公告)日：1997-09-02
申请号：US589793
申请日：1996-01-22
CPC分类号： G06F11/1666 , G06F11/1415 , G11C29/74 , G06F11/0754 , G06F11/20
摘要： A power loss detection and recovery circuit for providing continued memory operations upon loss of a supply voltage. Multiple independent power domains, each of which provides an electrically isolated supply voltage, are used to provide power to redundant memory circuitry. A loss of voltage or a degenerative voltage within a power domain is detected, and circuitry residing on a different operational power domain provides recovery operations to allow continued memory activity within that operational power domain. The memories residing in an adjacent pair of power domains redundant, and are therefore written to and read from simultaneously, and circuitry within an operational power domain will prevent further reading of data from the memory residing in a failed power domain, and will also prevent further writing of data to the memory residing in the failed power domain upon recognition of a failed supply voltage within a power domain.
摘要翻译： 一种功率损耗检测和恢复电路，用于在电源电压丢失时提供持续的存储器操作。 多个独立的电源域（每个都提供电隔离的电源电压）用于为冗余存储器电路提供电力。 检测到功率域内的电压损耗或退化电压，并且驻留在不同操作功率域的电路提供恢复操作，以允许在该操作功率域内的持续存储器活动。 驻留在相邻电源域对中的存储器是冗余的，并且因此被写入并被同时读取，并且操作功率域内的电路将阻止来自驻留在故障功率域中的存储器的数据的进一步读取，并且还将进一步防止 在识别出功率域内的故障电源电压时，将数据写入存在于故障电源域中的存储器。
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23.发明授权Processor communications bus having address lines selecting different storage locations based on selected control lines 失效处理器通信总线，其具有基于所选择的控制线选择不同存储位置的地址线
公开(公告)号：US5519876A
公开(公告)日：1996-05-21
申请号：US172629
申请日：1993-12-23
CPC分类号： G06F12/063
摘要： A bus architecture includes address lines, data lines, and control signals to allow a processor to communicate with a VLSI gate array. The address lines are interpreted by the VLSI gate array to select either multi-bit registers or single bit designators resident on the VLSI gate array depending on which control signal is received from the processor. Dual address decode logic on the VLSI gate array senses control signals indicating a request to read from a register, write to a register, and set, clear, or test a designator, and decodes the address received to select the appropriate storage location for the requested function.
摘要翻译： 总线架构包括地址线，数据线和控制信号，以允许处理器与VLSI门阵列通信。 地址线由VLSI门阵列解释，以根据从处理器接收的控制信号来选择驻留在VLSI门阵列上的多位寄存器或单位指示符。 VLSI门阵列上的双地址解码逻辑检测指示从寄存器读取，写入寄存器，设置，清除或测试指示符的请求的控制信号，并解码所接收的地址，以选择所请求的适当存储位置 功能。
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公开(公告)号：US5495598A
公开(公告)日：1996-02-27
申请号：US173598
申请日：1993-12-23
IPC分类号： G06F9/32 , G06F9/38 , G06F11/267 , G06F11/00 , H03M13/00
CPC分类号： G06F9/3804 , G06F11/2236 , G06F9/30058 , G06F9/30094
摘要： A method and apparatus for detecting stuck faults in a signal line used to communicate a branch condition for executing conditional branch instructions by a data processing system containing a programmable microprocessor and multiple VLSI gate arrays connected by a bi-directional bus, whereby the branch condition is obtained from a storage location resident on a VLSI gate array executing asynchronous and external to the microprocessor. The branch condition is fetched and evaluated in parallel with the fetching of the branch target address and the incrementing of the program counter. The microprocessor changes instruction sequence control depending on the results of the branch condition evaluation. The branch condition is sent to the microprocessor as a signal pulse for a specified duration at a particular time, rather than by changing the level of the signal, thereby allowing communication of the branch condition over only one signal line but still providing for detection of faults in the VSLI gate array or faults inherent in the signal line.
摘要翻译： 一种用于检测用于通过包含可编程微处理器的数据处理系统和由双向总线连接的多个VLSI门阵列来传送用于执行条件转移指令的分支条件的信号线中的卡死故障的方法和装置，由此分支条件是 从驻留在执行异步并在微处理器外部的VLSI门阵列上的存储位置获得。 分支条件与分支目标地址的获取和程序计数器的递增并行获取和评估。 微处理器根据分支条件评估的结果改变指令序列控制。 分支条件作为特定时间的指定持续时间的信号脉冲发送到微处理器，而不是通过改变信号的电平，从而允许在仅一条信号线上通信分支条件，但仍然提供故障的检测 在VSLI门阵列或信号线固有的故障。
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公开(公告)号：US5416362A
公开(公告)日：1995-05-16
申请号：US119957
申请日：1993-09-10
CPC分类号： H03K3/0372
摘要： An apparatus for a transparent master/slave flip-flop logic circuit including a single line connected to the transparency input of the logic macro so that when the line is active input data will pass through the flip-flop, unless the scan signal is also active, in which case the flip-flop will return to a clocked (latching) status.
摘要翻译： 一种用于透明主/从触发器逻辑电路的装置，包括连接到逻辑宏的透明度输入的单线，使得当线是有源时，输入数据将通过触发器，除非扫描信号也是有效的 在这种情况下，触发器将返回到时钟（锁存）状态。
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公开(公告)号：US4996688A
公开(公告)日：1991-02-26
申请号：US246512
申请日：1988-09-19
IPC分类号： G01R31/3185 , G06F11/00 , G06F11/26 , G06F11/273
CPC分类号： G01R31/318536 , G01R31/318569 , G06F11/261 , G06F11/2736
摘要： Apparatus for detecting and isolating the occurrence of faults in a digital electronic system so as to reduce the mean-time-to-repair. Associated with the logic circuitry to be monitored is a fault indicator which produces a fault signal when a malfunction occurs. Fault capture circuitry is arranged in a hierarchical manner and provides a group fault output signal when one of the fault indicators generates a fault signal. A programmable controller is provided which receives the group fault signal as an interrupt and which then responds by transferring registered fault event signals to a dynamic string register, rearming the error detection used to trap a fault signal and logging the fault location in a memory for later readout by a maintenance processor or the like. The dynamic string allows communications to take place using a scan/set protocol.
摘要翻译： 用于检测和隔离数字电子系统中的故障发生的装置，以便减少平均修复时间。 与待监控的逻辑电路相关联的是故障指示器，当故障发生时产生故障信号。 故障捕获电路以分层方式布置，并且当其中一个故障指示器产生故障信号时提供组故障输出信号。 提供了可编程控制器，其接收组故障信号作为中断，然后通过将注册的故障事件信号传送到动态串寄存器来进行响应，重新布置用于捕获故障信号的错误检测并将故障位置记录在存储器中以供以后 由维护处理器等读出。 动态字符串允许使用扫描/集合协议进行通信。
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公开(公告)号：US4962501A
公开(公告)日：1990-10-09
申请号：US244187
申请日：1988-09-13
IPC分类号： G06F11/10 , G06F11/267 , G06F13/00
CPC分类号： G06F11/10 , G06F11/2215
摘要： A plurality of transmitting and receiving elements are coupled between read and write buses. The communication paths which connects the tranmitting and receiving elements to the buses are each provided with a fault indicating circuit in series therewith. Each of said fault indicating circuits have logic gating means which include a bit register for each of the bits of a data byte and a parity bit. The output of the bit register means are coupled to isolation drivers which in turn are connected to parity checking circuits and the buses for indicating errors which occur in the bytes of a data word without degrading or delaying data transmission to and from said read and write buses.
摘要翻译： 多个发送和接收元件耦合在读和总线之间。 将发送和接收元件连接到总线的通信路径分别设置有与其串联的故障指示电路。 每个所述故障指示电路具有逻辑门控装置，其包括用于数据字节的每个比特的位寄存器和奇偶校验位。 位寄存器装置的输出耦合到隔离驱动器，隔离驱动器又连接到奇偶校验电路和总线，用于指示出现在数据字的字节中的错误，而不降低或延迟与所述读和写总线之间的数据传输 。
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公开(公告)号：US4953167A
公开(公告)日：1990-08-28
申请号：US244190
申请日：1988-09-13
CPC分类号： G06F11/085
摘要： Logic checking circuits are provided for verifying whether or not the data bus enable logic circuits are operating properly in response to operational commands to transmit or to NOT transmit data. The transmit latches in the bus interface logic circuits are continuously monitored to determine if they are set or NOT set in a position to enable transmission of data or NOT to enable transmission of data to a bus. Transmit gating circuit means are couple to the output of said transmit latches for determining if all of the transmit latches are in the same state and are in the state ordered by the central controller, and for determining whether the state ordered by the central controller occurs in the exact time period during which the command to transmit should be executed.
摘要翻译： 逻辑检查电路被提供用于验证数据总线使能逻辑电路是否响应于要发送或不发送数据的操作命令而正常工作。 总线接口逻辑电路中的发送锁存器被连续地监视，以确定它们是被设置还是不被设置在能够传输数据或不使数据传输到总线的位置。 发送门控电路装置耦合到所述发送锁存器的输出端，用于确定所有发送锁存器是否处于相同状态并且处于由中央控制器排序的状态，并且用于确定由中央控制器排序的状态是否发生在 应执行发送命令的确切时间段。
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公开(公告)号：US4953131A
公开(公告)日：1990-08-28
申请号：US241421
申请日：1988-09-07
IPC分类号： G11C11/406
CPC分类号： G11C11/406
摘要： A novel unconditional clock and automatic refresh logic system is provided which comprises a source of unconditional clock pulses coupled to the memory control logic in a manner which permits automatic refreshing of a dynamic memory. There is further provided clock logic means which sense the conditions in the dynamic memory system during which the dynamic memory is not being refreshed. There is further provided, means for generating automatic clock refresh signals coupled to the memory control logic for initiating continuous automatic refresh cycles when the system clock is being shutdown.
摘要翻译： 提供了一种新颖的无条件时钟和自动刷新逻辑系统，其包括以允许自动刷新动态存储器的方式耦合到存储器控制逻辑的无条件时钟脉冲的源。 还提供了时钟逻辑装置，其感测动态存储器系统中的动态存储器未被刷新的条件。 还提供了用于产生与存储器控制逻辑耦合的自动时钟刷新信号的装置，用于当系统时钟被关闭时发起连续的自动刷新周期。
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公开(公告)号：US4736292A
公开(公告)日：1988-04-05
申请号：US809681
申请日：1985-12-16
摘要： A series of instructions N, N+1, N+2, etc. are issued by an instruction buffer 14 at a fixed clock rate in a pipelined method to parallel instruction flow path 6 and control word flow path 8, each path including a serial coupled holding register 20, 21, an instruction register 18, 19 and a function register 16, 17. If instruction N is a jump instruction, it and the related control word, when stored in the function registers 16, 17 causes the jump target instruction and the related control word of the jump instruction N to be entered into the holding register 20, 21. If the jump instruction N jump conditions are satisfied, the jump target instruction and related control word are written into the instruction registers 18, 19 and then into the function registers 16, 17 to be executed by the associated system.
摘要翻译： 一条指令N，N + 1，N + 2等由指令缓冲器14以流水线方式以固定的时钟速率发送到并行指令流程6和控制字流程8，每条路径包括串行 耦合保持寄存器20,21，指令寄存器18,19和功能寄存器16,17。如果指令N是跳转指令，则该指令和相关控制字在存储在功能寄存器16,17中时导致跳转目标指令 以及要输入到保持寄存器20,21中的跳转指令N的相关控制字。如果跳转指令N跳转条件满足，则跳转目标指令和相关控制字被写入指令寄存器18,19，然后 进入由相关联的系统执行的功能寄存器16,17。
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