公开(公告)号：US4736292A

公开(公告)日：1988-04-05

申请号：US809681

申请日：1985-12-16

申请人： Michael Danilenko ,  Larry L. Byers ,  Louis B. Bushard

发明人： Michael Danilenko ,  Larry L. Byers ,  Louis B. Bushard

IPC分类号： G06F9/26 ,  G06F9/28 ,  G06F9/22

CPC分类号： G06F9/28 ,  G06F9/264

摘要： A series of instructions N, N+1, N+2, etc. are issued by an instruction buffer 14 at a fixed clock rate in a pipelined method to parallel instruction flow path 6 and control word flow path 8, each path including a serial coupled holding register 20, 21, an instruction register 18, 19 and a function register 16, 17. If instruction N is a jump instruction, it and the related control word, when stored in the function registers 16, 17 causes the jump target instruction and the related control word of the jump instruction N to be entered into the holding register 20, 21. If the jump instruction N jump conditions are satisfied, the jump target instruction and related control word are written into the instruction registers 18, 19 and then into the function registers 16, 17 to be executed by the associated system.

摘要翻译： 一条指令N，N + 1，N + 2等由指令缓冲器14以流水线方式以固定的时钟速率发送到并行指令流程6和控制字流程8，每条路径包括串行 耦合保持寄存器20,21，指令寄存器18,19和功能寄存器16,17。如果指令N是跳转指令，则该指令和相关控制字在存储在功能寄存器16,17中时导致跳转目标指令 以及要输入到保持寄存器20,21中的跳转指令N的相关控制字。如果跳转指令N跳转条件满足，则跳转目标指令和相关控制字被写入指令寄存器18,19，然后 进入由相关联的系统执行的功能寄存器16,17。

公开(公告)号：US4873630A

公开(公告)日：1989-10-10

申请号：US761201

申请日：1985-07-31

申请人： John T. Rusterholz ,  Archie E. Lahti ,  Louis B. Bushard ,  Larry L. Byers ,  James R. Hamstra ,  Charles J. Homan

发明人： John T. Rusterholz ,  Archie E. Lahti ,  Louis B. Bushard ,  Larry L. Byers ,  James R. Hamstra ,  Charles J. Homan

IPC分类号： F02B75/02 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/325 ,  F02B2075/025

摘要： An improved Scientific Processor for use in a data processing system having a general purpose host processor and a High Performance Storage Unit, and under operational control of the host processor is described. The Scientific Processor includes a Vector Processor Module and a Scalar Processor Module, each operable at comparable rates, wherein scalar operands and vector operands can be manipulated in various combinations under program control of an associated host processor, all without requirement of dedicated storage or caching. The Scalar Processor Module includes instruction flow control circuitry, loop control circuitry for controlling nested loops, and addressing circuitry for generating addresses to be referenced in the High Performance Storage Unit. A scalar processor arithmetic logic unit is described for performing scalar manipulations. The Vector Processor Module includes vector control circuitry and vector file storage circuitry together with vector file loading and vector storage circuitry. A plurality of vector manipulating pipelines for performing instruction functions of vector addition, vector multiplication and vector move is described wherein the pipelined functions can occur simultaneously, and each pipeline is capable of providing resultant operand pairs at a rate approximately equal to the reference cycle of the High Performance Storage Unit.

摘要翻译： 描述了一种用于具有通用主机处理器和高性能存储单元的数据处理系统的改进的科学处理器，并且在主处理器的操作控制下。 科学处理器包括一个矢量处理器模块和一个标量处理器模块，每个处理器模块以可比较的速率运行，其中标量操作数和矢量操作数可以在相关主机处理器的程序控制下以不同的组合进行操作，而不需要专门的存储或缓存。 标量处理器模块包括指令流控制电路，用于控制嵌套循环的环路控制电路，以及用于生成要在高性能存储单元中引用的地址的寻址电路。 描述了用于执行标量操作的标量处理器算术逻辑单元。 矢量处理器模块包括矢量控制电路和矢量文件存储电路以及矢量文件加载和矢量存储电路。 描述了用于执行向量相加，向量乘法和向量移动的指令功能的多个向量操纵流水线，其中流水线函数可以同时发生，并且每个流水线能够以大约等于 高性能存储单元。

公开(公告)号：US07853747B2

公开(公告)日：2010-12-14

申请号：US11803458

申请日：2007-05-15

申请人： Larry L. Byers ,  Joseba M. Desubijana ,  Gary R. Robeck ,  Fredarico E. Dutton

发明人： Larry L. Byers ,  Joseba M. Desubijana ,  Gary R. Robeck ,  Fredarico E. Dutton

IPC分类号： G06F13/14

CPC分类号： G06F3/0674 ,  G06F3/0626 ,  G06F3/0658 ,  G06F2213/0038

摘要： An embedded disk controller comprises a first processor in communication with a first bus and a second processor in communication with a second bus. An external bus controller (“EBC”) is located on the embedded disk controller, is coupled to an external bus and to at least one of the first bus and the second bus, and manages a plurality of memory devices external to the embedded disk controller via the external bus. A first one of the plurality of memory devices has at least one of different timing characteristics and a different data width than a second one of the plurality of memory devices.

摘要翻译： 嵌入式盘控制器包括与第一总线通信的第一处理器和与第二总线通信的第二处理器。 外部总线控制器（“EBC”）位于嵌入式磁盘控制器上，耦合到外部总线和第一总线和第二总线中的至少一个，并管理嵌入式磁盘控制器外部的多个存储器件 通过外部总线。 多个存储器件中的第一个具有与多个存储器件中的第二个不同的定时特性和不同数据宽度中的至少一个。

公开(公告)号：US07080188B2

公开(公告)日：2006-07-18

申请号：US10385022

申请日：2003-03-10

申请人： Larry L. Byers ,  Paul B. Ricci ,  Joseph G. Kriscunas ,  Joseba M. Desubijana ,  Gary R. Robeck ,  Michael R. Spaur ,  David M. Purdham

发明人： Larry L. Byers ,  Paul B. Ricci ,  Joseph G. Kriscunas ,  Joseba M. Desubijana ,  Gary R. Robeck ,  Michael R. Spaur ,  David M. Purdham

IPC分类号： G06F13/36 ,  G06F13/24

CPC分类号： G06F3/0674 ,  G06F3/0626 ,  G06F3/0658 ,  G06F2213/0038

摘要： A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.

摘要翻译： 提供了一种嵌入式磁盘控制器的系统。 该系统包括可操作地耦合到高性能总线的第一主处理器; 操作地耦合到外围总线的第二处理器; 高性能和外设总线之间的接口桥; 外部总线控制器，耦合到高性能总线，并通过外部总线接口可操作地耦合到外部设备; 中断控制器模块，其可以向第一主处理器产生快速中断; 耦合到高性能和外围总线的历史模块，用于监视总线活动; 以及伺服控制器，其通过伺服控制器接口耦合到第二处理器，并向第二处理器提供实时伺服控制器信息。 第二处理器可以是通过接口可操作地耦合到第一主处理器的数字信号处理器。

公开(公告)号：US5784712A

公开(公告)日：1998-07-21

申请号：US396677

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier

发明人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier

IPC分类号： G06F9/312 ,  G06F9/345 ,  G06F13/16 ,  G06F9/32

CPC分类号： G06F9/30043 ,  G06F13/1631 ,  G06F9/345 ,  G06F9/3861

摘要： A method and apparatus for efficiently reading or writing a number of successive address locations within a memory. In an exemplary embodiment, a processor or the like may not be required to provide an address to a memory unit for each read and/or write operation when successive address locations are accessed. That is, for multiple memory accesses which access successive address locations, the processor or the like may provide an initial address but thereafter may not be required to provide subsequent addresses to the memory unit. The subsequent addresses may be automatically generated by an automatic-increment block.

摘要翻译： 一种用于有效地读取或写入存储器内的多个连续地址位置的方法和装置。 在示例性实施例中，当访问连续的地址位置时，可能不需要处理器等来为每个读取和/或写入操作向存储器单元提供地址。 也就是说，对于访问连续地址位置的多个存储器访问，处理器等可以提供初始地址，但此后可能不需要向存储器单元提供后续地址。 随后的地址可以由自动增量块自动生成。

公开(公告)号：US5784393A

公开(公告)日：1998-07-21

申请号：US396680

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Ronald W. Splett

发明人： Larry L. Byers ,  Gary R. Robeck ,  Ronald W. Splett

IPC分类号： G06F11/10

CPC分类号： G06F11/10

摘要： A method and apparatus for providing fault detection to a corresponding bus when one or more of the users connected to the bus does not have a fault detection capability provided therein. Further, the present invention may provide a method and apparatus for performing fault detection on a corresponding bus when the width of the bus is insufficient to accommodate a number of parity bits. In an exemplary embodiment, a selected one of the number of users may validate all bus transmissions via a number of transceivers, regardless of which user has a fault detection capability provided therein. In another exemplary embodiment of the present invention, a transmitting user may provide a data word and a number of corresponding parity bits. The transmitting user may provide the data word to the bus while storing the corresponding number of parity bits therein. The data word may be provided back to the transmitting user via the corresponding transceivers wherein the transmitting user may check the data word against the number of parity bits previously generated by the transmitting user.

摘要翻译： 当连接到总线的一个或多个用户不具有其中提供的故障检测能力时，向相应总线提供故障检测的方法和装置。 此外，本发明可以提供一种用于当总线的宽度不足以容纳多个奇偶校验位时在相应总线上执行故障检测的方法和装置。 在示例性实施例中，所选择的一个用户可以经由多个收发器验证所有总线传输，而不管哪个用户具有其中提供的故障检测能力。 在本发明的另一示例性实施例中，发送用户可以提供数据字和多个对应的奇偶校验位。 发送用户可以在存储相应数量的奇偶校验位的同时向总线提供数据字。 数据字可以经由相应的收发器提供给发送用户，其中发送用户可以根据发送用户先前生成的奇偶校验位的数量来检查数据字。

公开(公告)号：US5680537A

公开(公告)日：1997-10-21

申请号：US396678

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier ,  John A. Miller

发明人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier ,  John A. Miller

IPC分类号： G06F11/22 ,  G06F13/00

CPC分类号： G06F11/2268

摘要： A method and apparatus for isolating an error in a system having a controller or the like which access a user via an interface device. The controller or the like may be coupled to the interface device via a first bus and the interface device may be coupled to the user via a second bus. The controller or the like may detect an error in a data transfer from the user to the controller via the interface device, and may isolate the error to the second bus/interface device or the first bus/controller. This up-front error isolation may reduce the amount of analysis required by a service technician after a corresponding PC board or the like is removed from the system, thereby reducing the cost thereof.

摘要翻译： 一种用于隔离具有通过接口设备访问用户的控制器等的系统中的错误的方法和装置。 控制器等可以经由第一总线耦合到接口设备，并且接口设备可以经由第二总线耦合到用户。 控制器等可以通过接口设备检测从用户到控制器的数据传输中的错误，并且可以将错误与第二总线/接口设备或第一总线/控制器隔离。 这种前期错误隔离可以减少在从系统移除相应的PC板等之后服务技术人员所需的分析量，从而降低其成本。

公开(公告)号：US5422915A

公开(公告)日：1995-06-06

申请号：US172661

申请日：1993-12-23

申请人： Larry L. Byers ,  Thomas T. Kubista ,  Gregory B. Wiedenman

发明人： Larry L. Byers ,  Thomas T. Kubista ,  Gregory B. Wiedenman

IPC分类号： G06F1/12 ,  G06F11/16 ,  H02J9/06 ,  H04J3/06 ,  H04L7/04 ,  H04L7/00

CPC分类号： G06F11/1604 ,  G06F1/12 ,  H02J9/06 ,  G06F11/20 ,  H04J3/0688 ,  Y10T307/62

摘要： A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop. Error recovery circuitry monitors for proper synchronization of the synchronized clock signals, and provides for automatic or manual error recovery upon detection of a synchronization error. A single phase synchronized clock signal is generated to minimize synchronization complexities, and circuitry exists at the circuit loads to generate multiple phase enable signals to emulate a multiple phase clock.

摘要翻译： 一种用于向多个电路负载提供同步时钟信号的容错多相时钟分配系统。 多个电隔离的电源域由冗余的交流和直流电源电路供电，以确保在交流或直流电源电路部分故障时持续运行。 来自多个电源域的多个振荡器被同步以产生一组同时同步的时钟信号。 然后由选择电路和选择控制电路选择来自该组的多个同步时钟信号，并分配给需要同步同步的多个电路负载。 振荡器电路，同步电路，选择电路和分配电路都以冗余形式提供，使得任何电路的部分故障不会导致系统停止。 错误恢复电路监视同步时钟信号的正确同步，并在检测到同步错误时提供自动或手动错误恢复。 生成单相同步时钟信号以最小化同步复杂度，并且在电路负载处存在电路以产生多相启动信号以仿真多相时钟。

公开(公告)号：US5142629A

公开(公告)日：1992-08-25

申请号：US403640

申请日：1989-09-06

申请人： Larry L. Byers ,  Joseba M. Desubijana

发明人： Larry L. Byers ,  Joseba M. Desubijana

IPC分类号： G06F13/40 ,  G06F15/173

CPC分类号： G06F15/17368 ,  G06F13/4022

摘要： An improved system for interconnecting main storage units is provided wherein each main storage unit is provided with a support control card and each support control card is provided with interface connection means comprising X-1 number of interfaces where X is a value equal to the number of MSUs. And means for enabling the connection of the interfaces between different pairs of MSUs to operably connect any number of said X number of MSUs to a plurality of data processors employing X(X-1)/2 pairs of cables.

摘要翻译： 提供了一种用于互连主存储单元的改进的系统，其中每个主存储单元设置有支持控制卡，并且每个支持控制卡设置有包括X-1个接口的接口连接装置，其中X等于 MSU。 以及用于使得能够连接不同成对MSU之间的接口的装置可操作地将任何数量的所述X个数量的MSU连接到采用X（X-1）/ 2对电缆的多个数据处理器。

公开(公告)号：US07457903B2

公开(公告)日：2008-11-25

申请号：US10384991

申请日：2003-03-10

申请人： David M. Purdham ,  Larry L. Byers ,  Andrew Artz

发明人： David M. Purdham ,  Larry L. Byers ,  Andrew Artz

IPC分类号： G06F13/14

CPC分类号： G06F3/0674 ,  G06F3/0626 ,  G06F3/0658 ,  G06F2213/0038

摘要： A method and system for generating interrupts in an embedded disk controller is provided. The method includes receiving vector values for an interrupt; determining if an interrupt request is pending; comparing the received vector value with a vector value of the pending interrupt; and replacing a previous vector value with the received vector value if the received vector value has higher priority. The system includes, at least one register for storing a trigger mode value which specifies whether an interrupt is edge triggered or level sensitive, and a vector address field that specifies a priority and address for an interrupt, and a mask value which masks an interrupt source. Also provided is a method for generating a fast interrupt. The method includes, receiving an input signal from a fast interrupt source; and generating a fast interrupt signal based on priority and a mask signal.

摘要翻译： 提供了一种用于在嵌入式磁盘控制器中产生中断的方法和系统。 该方法包括接收中断的向量值; 确定中断请求是否正在等待; 将接收到的矢量值与未决中断的向量值进行比较; 并且如果接收到的向量值具有较高的优先级，则用接收的向量值替换先前的向量值。 该系统包括至少一个用于存储指定中断是边缘触发还是电平敏感的触发模式值的寄存器以及指定中断的优先级和地址的向量地址字段以及屏蔽中断源的掩码值 。 还提供了一种用于产生快速中断的方法。 该方法包括：从快速中断源接收输入信号; 以及基于优先级和掩码信号产生快速中断信号。