公开(公告)号：US4996688A

公开(公告)日：1991-02-26

申请号：US246512

申请日：1988-09-19

申请人： Larry L. Byers ,  Kay Tsang ,  James H. Scheuneman ,  Penny Svenkeson

发明人： Larry L. Byers ,  Kay Tsang ,  James H. Scheuneman ,  Penny Svenkeson

IPC分类号： G01R31/3185 ,  G06F11/00 ,  G06F11/26 ,  G06F11/273

CPC分类号： G01R31/318536 ,  G01R31/318569 ,  G06F11/261 ,  G06F11/2736

摘要： Apparatus for detecting and isolating the occurrence of faults in a digital electronic system so as to reduce the mean-time-to-repair. Associated with the logic circuitry to be monitored is a fault indicator which produces a fault signal when a malfunction occurs. Fault capture circuitry is arranged in a hierarchical manner and provides a group fault output signal when one of the fault indicators generates a fault signal. A programmable controller is provided which receives the group fault signal as an interrupt and which then responds by transferring registered fault event signals to a dynamic string register, rearming the error detection used to trap a fault signal and logging the fault location in a memory for later readout by a maintenance processor or the like. The dynamic string allows communications to take place using a scan/set protocol.

摘要翻译： 用于检测和隔离数字电子系统中的故障发生的装置，以便减少平均修复时间。 与待监控的逻辑电路相关联的是故障指示器，当故障发生时产生故障信号。 故障捕获电路以分层方式布置，并且当其中一个故障指示器产生故障信号时提供组故障输出信号。 提供了可编程控制器，其接收组故障信号作为中断，然后通过将注册的故障事件信号传送到动态串寄存器来进行响应，重新布置用于捕获故障信号的错误检测并将故障位置记录在存储器中以供以后 由维护处理器等读出。 动态字符串允许使用扫描/集合协议进行通信。

公开(公告)号：US5060145A

公开(公告)日：1991-10-22

申请号：US403624

申请日：1989-09-06

申请人： James H. Scheuneman ,  Larry L. Byers ,  Wayne A. Michaelson

发明人： James H. Scheuneman ,  Larry L. Byers ,  Wayne A. Michaelson

IPC分类号： G06F13/372 ,  G11C7/10 ,  G11C8/12

CPC分类号： G11C7/1063 ,  G06F13/372 ,  G11C7/1039 ,  G11C8/12

摘要： A novel memory access system is provided for simultaneously processing request for access to a plurality of memory banks. A plurality of input-output ports are coupled to a read bus and to a write bus which are in turn coupled to the memory banks to be accessed by read and write commands initiated by processors coupled to the I/O ports. Pipeline control means receive the request for access functions from the processors and are operable to resolve conflict between plural request. The pipeline control means sequentially raise either write or read request on control and address buses and generate time slot windows during which subsequent write or read data transfer operations will occur so that data being pipelined on the write and read buses is being simultaneously accessed.

摘要翻译： 提供了一种新颖的存储器访问系统，用于同时处理对多个存储体的访问请求。 多个输入 - 输出端口耦合到读总线和写总线，写总线又耦合到存储器组，以通过由耦合到I / O端口的处理器发起的读写命令来访问。 管道控制装置从处理器接收对访问功能的请求，并且可操作地解决多个请求之间的冲突。 流水线控制装置顺序地在控制和地址总线上提高写入或读取请求，并产生时隙窗口，在此期间将发生随后的写入或读取数据传输操作，从而正在同时访问在写入和读取总线上被流水线化的数据。

公开(公告)号：US4962501A

公开(公告)日：1990-10-09

申请号：US244187

申请日：1988-09-13

申请人： Larry L. Byers ,  James H. Scheuneman ,  Joseba M. Desubijana

发明人： Larry L. Byers ,  James H. Scheuneman ,  Joseba M. Desubijana

IPC分类号： G06F11/10 ,  G06F11/267 ,  G06F13/00

CPC分类号： G06F11/10 ,  G06F11/2215

摘要： A plurality of transmitting and receiving elements are coupled between read and write buses. The communication paths which connects the tranmitting and receiving elements to the buses are each provided with a fault indicating circuit in series therewith. Each of said fault indicating circuits have logic gating means which include a bit register for each of the bits of a data byte and a parity bit. The output of the bit register means are coupled to isolation drivers which in turn are connected to parity checking circuits and the buses for indicating errors which occur in the bytes of a data word without degrading or delaying data transmission to and from said read and write buses.

摘要翻译： 多个发送和接收元件耦合在读和总线之间。 将发送和接收元件连接到总线的通信路径分别设置有与其串联的故障指示电路。 每个所述故障指示电路具有逻辑门控装置，其包括用于数据字节的每个比特的位寄存器和奇偶校验位。 位寄存器装置的输出耦合到隔离驱动器，隔离驱动器又连接到奇偶校验电路和总线，用于指示出现在数据字的字节中的错误，而不降低或延迟与所述读和写总线之间的数据传输 。

公开(公告)号：US4953131A

公开(公告)日：1990-08-28

申请号：US241421

申请日：1988-09-07

申请人： David M. Purdham ,  James H. Scheuneman ,  Larry L. Byers ,  Terence Sych ,  Kwisook Tsang

发明人： David M. Purdham ,  James H. Scheuneman ,  Larry L. Byers ,  Terence Sych ,  Kwisook Tsang

IPC分类号： G11C11/406

CPC分类号： G11C11/406

摘要： A novel unconditional clock and automatic refresh logic system is provided which comprises a source of unconditional clock pulses coupled to the memory control logic in a manner which permits automatic refreshing of a dynamic memory. There is further provided clock logic means which sense the conditions in the dynamic memory system during which the dynamic memory is not being refreshed. There is further provided, means for generating automatic clock refresh signals coupled to the memory control logic for initiating continuous automatic refresh cycles when the system clock is being shutdown.

摘要翻译： 提供了一种新颖的无条件时钟和自动刷新逻辑系统，其包括以允许自动刷新动态存储器的方式耦合到存储器控制逻辑的无条件时钟脉冲的源。 还提供了时钟逻辑装置，其感测动态存储器系统中的动态存储器未被刷新的条件。 还提供了用于产生与存储器控制逻辑耦合的自动时钟刷新信号的装置，用于当系统时钟被关闭时发起连续的自动刷新周期。

公开(公告)号：US07853747B2

公开(公告)日：2010-12-14

申请号：US11803458

申请日：2007-05-15

申请人： Larry L. Byers ,  Joseba M. Desubijana ,  Gary R. Robeck ,  Fredarico E. Dutton

发明人： Larry L. Byers ,  Joseba M. Desubijana ,  Gary R. Robeck ,  Fredarico E. Dutton

IPC分类号： G06F13/14

CPC分类号： G06F3/0674 ,  G06F3/0626 ,  G06F3/0658 ,  G06F2213/0038

摘要： An embedded disk controller comprises a first processor in communication with a first bus and a second processor in communication with a second bus. An external bus controller (“EBC”) is located on the embedded disk controller, is coupled to an external bus and to at least one of the first bus and the second bus, and manages a plurality of memory devices external to the embedded disk controller via the external bus. A first one of the plurality of memory devices has at least one of different timing characteristics and a different data width than a second one of the plurality of memory devices.

摘要翻译： 嵌入式盘控制器包括与第一总线通信的第一处理器和与第二总线通信的第二处理器。 外部总线控制器（“EBC”）位于嵌入式磁盘控制器上，耦合到外部总线和第一总线和第二总线中的至少一个，并管理嵌入式磁盘控制器外部的多个存储器件 通过外部总线。 多个存储器件中的第一个具有与多个存储器件中的第二个不同的定时特性和不同数据宽度中的至少一个。

公开(公告)号：US07080188B2

公开(公告)日：2006-07-18

申请号：US10385022

申请日：2003-03-10

申请人： Larry L. Byers ,  Paul B. Ricci ,  Joseph G. Kriscunas ,  Joseba M. Desubijana ,  Gary R. Robeck ,  Michael R. Spaur ,  David M. Purdham

发明人： Larry L. Byers ,  Paul B. Ricci ,  Joseph G. Kriscunas ,  Joseba M. Desubijana ,  Gary R. Robeck ,  Michael R. Spaur ,  David M. Purdham

IPC分类号： G06F13/36 ,  G06F13/24

CPC分类号： G06F3/0674 ,  G06F3/0626 ,  G06F3/0658 ,  G06F2213/0038

摘要： A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.

摘要翻译： 提供了一种嵌入式磁盘控制器的系统。 该系统包括可操作地耦合到高性能总线的第一主处理器; 操作地耦合到外围总线的第二处理器; 高性能和外设总线之间的接口桥; 外部总线控制器，耦合到高性能总线，并通过外部总线接口可操作地耦合到外部设备; 中断控制器模块，其可以向第一主处理器产生快速中断; 耦合到高性能和外围总线的历史模块，用于监视总线活动; 以及伺服控制器，其通过伺服控制器接口耦合到第二处理器，并向第二处理器提供实时伺服控制器信息。 第二处理器可以是通过接口可操作地耦合到第一主处理器的数字信号处理器。

公开(公告)号：US5784712A

公开(公告)日：1998-07-21

申请号：US396677

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier

发明人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier

IPC分类号： G06F9/312 ,  G06F9/345 ,  G06F13/16 ,  G06F9/32

CPC分类号： G06F9/30043 ,  G06F13/1631 ,  G06F9/345 ,  G06F9/3861

摘要： A method and apparatus for efficiently reading or writing a number of successive address locations within a memory. In an exemplary embodiment, a processor or the like may not be required to provide an address to a memory unit for each read and/or write operation when successive address locations are accessed. That is, for multiple memory accesses which access successive address locations, the processor or the like may provide an initial address but thereafter may not be required to provide subsequent addresses to the memory unit. The subsequent addresses may be automatically generated by an automatic-increment block.

摘要翻译： 一种用于有效地读取或写入存储器内的多个连续地址位置的方法和装置。 在示例性实施例中，当访问连续的地址位置时，可能不需要处理器等来为每个读取和/或写入操作向存储器单元提供地址。 也就是说，对于访问连续地址位置的多个存储器访问，处理器等可以提供初始地址，但此后可能不需要向存储器单元提供后续地址。 随后的地址可以由自动增量块自动生成。

公开(公告)号：US5784393A

公开(公告)日：1998-07-21

申请号：US396680

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Ronald W. Splett

发明人： Larry L. Byers ,  Gary R. Robeck ,  Ronald W. Splett

IPC分类号： G06F11/10

CPC分类号： G06F11/10

摘要： A method and apparatus for providing fault detection to a corresponding bus when one or more of the users connected to the bus does not have a fault detection capability provided therein. Further, the present invention may provide a method and apparatus for performing fault detection on a corresponding bus when the width of the bus is insufficient to accommodate a number of parity bits. In an exemplary embodiment, a selected one of the number of users may validate all bus transmissions via a number of transceivers, regardless of which user has a fault detection capability provided therein. In another exemplary embodiment of the present invention, a transmitting user may provide a data word and a number of corresponding parity bits. The transmitting user may provide the data word to the bus while storing the corresponding number of parity bits therein. The data word may be provided back to the transmitting user via the corresponding transceivers wherein the transmitting user may check the data word against the number of parity bits previously generated by the transmitting user.

摘要翻译： 当连接到总线的一个或多个用户不具有其中提供的故障检测能力时，向相应总线提供故障检测的方法和装置。 此外，本发明可以提供一种用于当总线的宽度不足以容纳多个奇偶校验位时在相应总线上执行故障检测的方法和装置。 在示例性实施例中，所选择的一个用户可以经由多个收发器验证所有总线传输，而不管哪个用户具有其中提供的故障检测能力。 在本发明的另一示例性实施例中，发送用户可以提供数据字和多个对应的奇偶校验位。 发送用户可以在存储相应数量的奇偶校验位的同时向总线提供数据字。 数据字可以经由相应的收发器提供给发送用户，其中发送用户可以根据发送用户先前生成的奇偶校验位的数量来检查数据字。

公开(公告)号：US5680537A

公开(公告)日：1997-10-21

申请号：US396678

申请日：1995-03-01

申请人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier ,  John A. Miller

发明人： Larry L. Byers ,  Gary R. Robeck ,  Terry J. Brunmeier ,  John A. Miller

IPC分类号： G06F11/22 ,  G06F13/00

CPC分类号： G06F11/2268

摘要： A method and apparatus for isolating an error in a system having a controller or the like which access a user via an interface device. The controller or the like may be coupled to the interface device via a first bus and the interface device may be coupled to the user via a second bus. The controller or the like may detect an error in a data transfer from the user to the controller via the interface device, and may isolate the error to the second bus/interface device or the first bus/controller. This up-front error isolation may reduce the amount of analysis required by a service technician after a corresponding PC board or the like is removed from the system, thereby reducing the cost thereof.

摘要翻译： 一种用于隔离具有通过接口设备访问用户的控制器等的系统中的错误的方法和装置。 控制器等可以经由第一总线耦合到接口设备，并且接口设备可以经由第二总线耦合到用户。 控制器等可以通过接口设备检测从用户到控制器的数据传输中的错误，并且可以将错误与第二总线/接口设备或第一总线/控制器隔离。 这种前期错误隔离可以减少在从系统移除相应的PC板等之后服务技术人员所需的分析量，从而降低其成本。

公开(公告)号：US5422915A

公开(公告)日：1995-06-06

申请号：US172661

申请日：1993-12-23

申请人： Larry L. Byers ,  Thomas T. Kubista ,  Gregory B. Wiedenman

发明人： Larry L. Byers ,  Thomas T. Kubista ,  Gregory B. Wiedenman

IPC分类号： G06F1/12 ,  G06F11/16 ,  H02J9/06 ,  H04J3/06 ,  H04L7/04 ,  H04L7/00

CPC分类号： G06F11/1604 ,  G06F1/12 ,  H02J9/06 ,  G06F11/20 ,  H04J3/0688 ,  Y10T307/62

摘要： A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop. Error recovery circuitry monitors for proper synchronization of the synchronized clock signals, and provides for automatic or manual error recovery upon detection of a synchronization error. A single phase synchronized clock signal is generated to minimize synchronization complexities, and circuitry exists at the circuit loads to generate multiple phase enable signals to emulate a multiple phase clock.

摘要翻译： 一种用于向多个电路负载提供同步时钟信号的容错多相时钟分配系统。 多个电隔离的电源域由冗余的交流和直流电源电路供电，以确保在交流或直流电源电路部分故障时持续运行。 来自多个电源域的多个振荡器被同步以产生一组同时同步的时钟信号。 然后由选择电路和选择控制电路选择来自该组的多个同步时钟信号，并分配给需要同步同步的多个电路负载。 振荡器电路，同步电路，选择电路和分配电路都以冗余形式提供，使得任何电路的部分故障不会导致系统停止。 错误恢复电路监视同步时钟信号的正确同步，并在检测到同步错误时提供自动或手动错误恢复。 生成单相同步时钟信号以最小化同步复杂度，并且在电路负载处存在电路以产生多相启动信号以仿真多相时钟。