Integrated circuit for preventing chip swapping and/or device cloning in a host device
    22.
    发明授权
    Integrated circuit for preventing chip swapping and/or device cloning in a host device 有权
    用于在主机设备中防止芯片交换和/或设备克隆的集成电路

    公开(公告)号:US08650633B2

    公开(公告)日:2014-02-11

    申请号:US13250529

    申请日:2011-09-30

    IPC分类号: G06F21/00

    摘要: An integrated circuit is disclosed that can be included in a host electronic device that can be commonly manufactured, where the integrated circuit can be designated (“locked”) for a specific manufacturer, thereby substantially reducing the likelihood that a third party will be able to successfully clone a host electronic device manufactured by the specific manufacturer and/or swap the chip containing the integrated circuit for one having more enabled features. The integrated circuit includes an ID module that can be programmed after fabrication. Components within the integrated circuit designate manufacturer-specific configurations (e.g., address mapping, pin routing and/or vital function releasing) based on the programmed manufacturer ID. As a result, once the integrated circuit has been programmed with the manufacturer ID, the integrated circuit will function correctly only within a host device manufactured by the manufacturer associated with the programmed manufacturer ID.

    摘要翻译: 公开了一种集成电路,其可以被包括在可以通常制造的主机电子设备中,其中可以为特定制造商指定(“锁定”)集成电路,从而显着降低第三方将能够 成功克隆由特定制造商制造的主机电子设备和/或将包含集成电路的芯片交换为具有更多启用特征的芯片。 集成电路包括可在制造后编程的ID模块。 集成电路中的组件基于编程的制造商ID指定制造商特定的配置(例如,地址映射,引脚布线和/或重要功能释放)。 因此,一旦集成电路已经用制造商ID编程,集成电路将仅在制造商制造的与编程的制造商ID相关联的主机设备中正常工作。

    Apparatus and method for partitioning, sandboxing and protecting external memories
    23.
    发明申请
    Apparatus and method for partitioning, sandboxing and protecting external memories 审中-公开
    用于分割,沙箱和保护外部存储器的装置和方法

    公开(公告)号:US20110191562A1

    公开(公告)日:2011-08-04

    申请号:US12714367

    申请日:2010-02-26

    IPC分类号: G06F12/14 G06F12/06

    CPC分类号: G06F12/06 G06F12/14

    摘要: A technique to provide an integrated circuit that performs memory partitioning to partition a memory into a plurality of regions, in which the memory is accessed by a plurality of heterogeneous processing devices that operate to access the memory. The integrated circuit also assigns a security level for each region of the memory and permits a memory access by a transaction to a particular region of the memory, only when a level of security assigned to the transaction meets or exceeds the assigned security level for the particular region. The integrated circuit also performs sandboxing by assigning which of the plurality of processing devices are permitted access to each of the plurality of regions. The integrated circuit may implement only the security level function or only the sandboxing function, or the integrated circuit may implement them both. In some instances, a scrambling/descrambling function is included to scramble/descramble data. In one application, the integrated circuit is included within a mobile phone.

    摘要翻译: 一种提供集成电路的技术,其执行存储器分区以将存储器分割成多个区域,其中存储器被操作以访问存储器的多个异构处理设备访问。 集成电路还为存储器的每个区域分配安全级别,并且仅当分配给事务的安全级满足或超过特定的分配的安全级别时才允许通过存储器的特定区域的事务的存储器访问 地区。 集成电路还通过分配多个处理设备中的哪一个被允许访问多个区域中的每一个来执行沙箱。 集成电路只能实现安全级别功能或仅实施沙盒功能,或者集成电路可以实现它们。 在一些情况下,加扰/解扰功能被包括以加扰/解扰数据。 在一个应用中,集成电路被包括在移动电话中。

    PROTECTING DATA ON INTEGRATED CIRCUIT
    24.
    发明申请
    PROTECTING DATA ON INTEGRATED CIRCUIT 有权
    集成电路保护数据

    公开(公告)号:US20100107023A1

    公开(公告)日:2010-04-29

    申请号:US12259903

    申请日:2008-10-28

    IPC分类号: G01R31/3185 G06F11/267

    CPC分类号: G01R31/31719

    摘要: Various example embodiments are disclosed. According to one example embodiment, an integrated circuit may include a mode block, a plurality of data blocks, and a reset node. The mode block may be configured to output a test mode signal, a scan mode signal, and a trigger signal based on a received data input. The plurality of data blocks may each include registers configured to store data, each of the plurality of data blocks being configured to write over at least some of the data stored in their respective registers in response to receiving a write-over instruction. The reset node may be configured to reset the registers based on receiving either a first reset input or a second reset input. The integrated circuit may be configured to enter a test mode, enter a scan mode, and exit the test mode.

    摘要翻译: 公开了各种示例性实施例。 根据一个示例实施例,集成电路可以包括模式块,多个数据块和复位节点。 模式块可以被配置为基于接收到的数据输入来输出测试模式信号,扫描模式信号和触发信号。 多个数据块可以各自包括被配置为存储数据的寄存器,所述多个数据块中的每一个被配置为响应于接收到写入指令而写入存储在它们各自寄存器中的至少一些数据。 复位节点可以被配置为基于接收到第一复位输入或第二复位输入来复位寄存器。 集成电路可以配置为进入测试模式,进入扫描模式,并退出测试模式。