公开(公告)号：US11277455B2

公开(公告)日：2022-03-15

申请号：US16430457

申请日：2019-06-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Alex Vainman ,  Natan Manevich ,  Nir Nitzani ,  Ilan Smith ,  Richard Hastie ,  Noam Bloch ,  Lior Narkis ,  Rafi Weiner

IPC: H04L29/06 ,  H04L12/861 ,  H04L12/851 ,  H04L12/841 ,  H04L12/801 ,  H04L12/823 ,  H04L65/613 ,  H04L65/80 ,  H04L67/01 ,  H04L49/90 ,  H04L47/2441 ,  H04L47/28 ,  H04L47/34 ,  H04L47/32 ,  H04L29/08 ,  H04L67/06

Abstract: A method including configuring a transmit process to store information including a queue of packets to be transmitted, the queue defining transmit process packets to be transmitted, each packet associated with a transmission time, and configuring a synchronization process to receive from the transmit process at least some of the information. The synchronization process performs one of: A) accessing a dummy send queue and a completion queue, and transmitting one or more of the transmit process packets in accordance with a completion queue entry in the completion queue, and B) sends a doorbell to transmission hardware at a time when at least one of the transmit process packets is to be transmitted, the synchronization process including a master queue configured to store transmission entries, each transmission entry including a transmit process indicator and an indication of transmit process packets to be transmitted. Related apparatus and methods are also described.

公开(公告)号：US11184439B2

公开(公告)日：2021-11-23

申请号：US16827912

申请日：2020-03-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Haggai Eran ,  Dotan David Levi ,  Maxim Fudim ,  Liran Liss

IPC: H04L29/08 ,  G06F13/28 ,  G06F15/173

Abstract: A network node includes a bus switching element, and a network adapter, an accelerator and a host, all coupled to communicate via the bus switching element. The network adapter is configured to communicate with remote nodes over a communication network. The host is configured to establish a RDMA link between the accelerator and the RDMA endpoint by creating a Queue Pair (QP) to be used by the accelerator for communication with the RDMA endpoint via the RDMA link. The accelerator is configured to exchange data, via the network adapter, between a memory of the accelerator and a memory of the RDMA endpoint.

公开(公告)号：US20210297151A1

公开(公告)日：2021-09-23

申请号：US16921993

申请日：2020-07-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula ,  Paraskevas Bakopoulos ,  Ariel Almog ,  Roee Moyal ,  Gal Yefet

IPC: H04B7/26 ,  H04W72/04 ,  H04W74/08 ,  H04L12/931 ,  H04L12/861

Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound. packets, which are received from the communication network, depending on the timeslots.

公开(公告)号：US20210243140A1

公开(公告)日：2021-08-05

申请号：US16782075

申请日：2020-02-05

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula

IPC: H04L12/861 ,  H04L29/06 ,  H04L12/741 ,  H04L12/46 ,  H04L12/931 ,  H04L12/801 ,  H04W56/00

Abstract: A network adapter includes a host interface configured to communicate with a host, a network interface configured to communicate with a communication network, and packet processing circuitry. The packet processing circuitry is configured to receive a packet from the host via the host interface, or from the communication network via the network interface, to receive an indication of a network time used for synchronizing network elements in the communication network, to match the packet to a rule, the rule including a condition and an action, and to perform the action in response to the packet meeting the condition, wherein one or more of (i) the condition in the rule and (ii) the action in the rule, depend on the network time.

公开(公告)号：US20210168354A1

公开(公告)日：2021-06-03

申请号：US17095765

申请日：2020-11-12

Applicant: MELLANOX TECHNOLOGIES, LTD. ,  BEAMR IMAGING LTD.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Ohad Markus ,  Uri Gadot ,  Aviad Raveh ,  Dror Gill ,  Nikolay Terterov ,  Pavel Titkov ,  Alexey Mitkovets ,  Alexey Martemyanov ,  Alexander Zheludkov

IPC: H04N19/105 ,  H04N19/119 ,  H04N19/159 ,  H04N19/51 ,  H04N19/176

Abstract: A video coding system including an acceleration device including input circuitry configured, for each of a first plurality of video frames to be encoded, to receive an input including at least one raw video frame and at least one reference frame, and to divide each of the first plurality of video frames to be encoded into a second plurality of blocks, and similarity computation circuitry configured, for each one of the first plurality of video frame to be encoded: for each the block of the second plurality of blocks, to produce an intra-prediction hint and an intra-prediction direction. Related apparatus and methods are also provided.

公开(公告)号：US20200092229A1

公开(公告)日：2020-03-19

申请号：US16693302

申请日：2019-11-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Avi Urman

IPC: H04L12/939 ,  H04L12/861 ,  H04L12/879 ,  H04L29/06 ,  H04W28/04

Abstract: Communication apparatus includes a host interface and a network interface, which receives from a packet communication network at least one packet stream including a sequence of data packets, which include headers containing respective sequence numbers and data payloads containing slices of the data segment having a predefined, fixed size per slice. Packet processing circuitry is configured to receive the data packets from the network interface, and to map the data payloads of the data packets in the at least one packet stream, using a linear mapping of the sequence numbers, to respective addresses in the buffer.

公开(公告)号：US12238273B2

公开(公告)日：2025-02-25

申请号：US17095765

申请日：2020-11-12

Applicant: MELLANOX TECHNOLOGIES, LTD. ,  BEAMR IMAGING LTD.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Ohad Markus ,  Uri Gadot ,  Aviad Raveh ,  Dror Gill ,  Nikolay Terterov ,  Pavel Titkov ,  Alexey Mitkovets ,  Alexey Martemyanov ,  Alexander Zheludkov

IPC: H04N19/105 ,  H04N19/119 ,  H04N19/159 ,  H04N19/176 ,  H04N19/51

Abstract: A video coding system including an acceleration device including input circuitry configured, for each of a first plurality of video frames to be encoded, to receive an input including at least one raw video frame and at least one reference frame, and to divide each of the first plurality of video frames to be encoded into a second plurality of blocks, and similarity computation circuitry configured, for each one of the first plurality of video frame to be encoded: for each the block of the second plurality of blocks, to produce an intra-prediction hint and an intra-prediction direction. Related apparatus and methods are also provided.

公开(公告)号：US20250023705A1

公开(公告)日：2025-01-16

申请号：US18219895

申请日：2023-07-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Thomas Kernen

IPC: H04L7/00

Abstract: A network device includes control logic coupled to a receiver. The control logic detects an synchronization packet received via the receiver from a second network device over a network that is precision time protocol unaware. The control logic determines that a portion of the synchronization packet is asserted, indicating that the synchronization packet has incurred congestion traversing the network. The control logic adjusts, based on an assertion of the portion, a weight applied to timestamps associated with sending and receiving the synchronization packet in performing clock synchronization with the second network device.

公开(公告)号：US20240244225A1

公开(公告)日：2024-07-18

申请号：US18096428

申请日：2023-01-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Eshed Ram ,  Dotan David Levi ,  Assaf Hallak ,  Shie Mannor ,  Gal Chechik ,  Eyal Frishman ,  Ohad Markus ,  Dror Porat ,  Assaf Weissman

IPC: H04N19/147 ,  H04N19/124 ,  H04N19/172

CPC classification number: H04N19/147 ,  H04N19/124 ,  H04N19/172

Abstract: A system includes a processing device to receive video content, metadata related to the video content, and a target bit rate for encoding the video content. The processing device further detects a content type of the video content based on the metadata and encodes hardware to perform frame encoding on the video content. The system further includes a controller coupled between the processing device and the encoding hardware. The controller is programmed with machine instructions to generate first QP values on a per-frame basis using a frame machine learning model with a first plurality of weights. The first plurality of weights depends at least in part on the content type and the target bit rate. The controller further provides the first QP values to the encoding hardware for rate control of the frame encoding.

公开(公告)号：US20240231984A9

公开(公告)日：2024-07-11

申请号：US18074751

申请日：2022-12-05

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Shay Aisman ,  Ariel Almog ,  Ran Avraham Koren

IPC: G06F11/07

CPC classification number: G06F11/0757 ,  G06F11/0736

Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.