公开(公告)号：US20220020736A1

公开(公告)日：2022-01-20

申请号：US16932098

申请日：2020-07-17

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Kunal R. Parekh ,  Akira Goda

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20210384354A1

公开(公告)日：2021-12-09

申请号：US16891462

申请日：2020-06-03

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Guangyu Huang ,  Haitao Liu ,  Akira Goda

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/11529

Abstract: A transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.

公开(公告)号：US11075163B2

公开(公告)日：2021-07-27

申请号：US14810044

申请日：2015-07-27

Applicant: Micron Technology, Inc.

Inventor： Koji Sakui ,  Peter Sean Feeley ,  Akira Goda

IPC: G11C16/04 ,  H01L23/528 ,  G11C11/56 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/532 ,  H01L23/535 ,  H01L29/49

Abstract: Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.

公开(公告)号：US20210217730A1

公开(公告)日：2021-07-15

申请号：US16742485

申请日：2020-01-14

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/482 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

公开(公告)号：US20210174874A1

公开(公告)日：2021-06-10

申请号：US17027425

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/34 ,  G11C16/12 ,  G11C16/14 ,  G11C16/06

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

公开(公告)号：US20210118508A1

公开(公告)日：2021-04-22

申请号：US17087166

申请日：2020-11-02

Applicant: Micron Technology, Inc.

Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  H01L45/00 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

公开(公告)号：US10777281B2

公开(公告)日：2020-09-15

申请号：US16227874

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Akira Goda

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11529 ,  G11C16/16 ,  H01L27/11565 ,  H01L27/11575 ,  G11C7/10

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a first pillar extending through the first group of conductive materials and the first group of dielectric materials, memory cells located along the first pillar, a conductive contact coupled to one of the conductive materials, and a second pillar extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, and a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion has a doping concentration less than a doping concentration of each of the first and fourth portions.

公开(公告)号：US10734399B2

公开(公告)日：2020-08-04

申请号：US15858509

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Jin Chen ,  Guangyu Huang ,  Mojtaba Asadirad

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11551 ,  H01L27/11526 ,  G11C16/26 ,  G11C16/24 ,  G11C16/14 ,  G11C16/10 ,  H01L23/528 ,  H01L29/36 ,  H01L29/04 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L23/532 ,  G11C16/08 ,  G11C16/04 ,  H01L29/08

Abstract: Some embodiments include apparatuses, and methods of forming the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a pillar extending through the conductive materials and the dielectric materials, memory cells located along the first pillar, a conductive contact coupled to a conductive material of the first group of conductive materials, and additional pillars extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion of each of the additional pillars is part of a piece of material extending from a first pillar to a second pillar of the additional pillars.

公开(公告)号：US20200227428A1

公开(公告)日：2020-07-16

申请号：US16248248

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/08 ,  H01L21/28 ,  H01L23/532

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

公开(公告)号：US20200066346A1

公开(公告)日：2020-02-27

申请号：US16667465

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  H01L45/00 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.