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公开(公告)号：US10909011B2
公开(公告)日：2021-02-02
申请号：US16161932
申请日：2018-10-16
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson
Abstract: Techniques are provided for storing a row address of a defective row of memory cells to a bank of non-volatile storage elements (e.g., fuses or anti-fuses). After a memory device has been packaged, one or more rows of memory cells may become defective. In order to repair (e.g., replace) the rows, a post-package repair (PPR) operation may occur to replace the defective row with a redundant row of the memory array. To replace the defective row with a redundant row, an address of the defective row may be stored (e.g., mapped) to an available bank of non-volatile storage elements that is associated with a redundant row. Based on the bank of non-volatile storage elements the address of the defective row, subsequent access operations may utilize the redundant row and not the defective row.
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公开(公告)号：US20200243158A1
公开(公告)日：2020-07-30
申请号：US16256796
申请日：2019-01-24
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Alan J. Wilson
IPC: G11C29/00 , G11C29/02 , G11C29/32 , G11C17/18 , G11C11/408 , G11C11/4076 , G11C7/22 , G11C7/10
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.
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公开(公告)号：US10403390B1
公开(公告)日：2019-09-03
申请号：US15948585
申请日：2018-04-09
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , John E. Riley
Abstract: Systems and methods to perform post-packaging repair of previously repaired data groups are disclosed. The devices may have an array of addressable rows or columns of memory cells, which can be activated. Upon identification of defect in a memory cell row or column, a repair in which the memory cell may be deactivated and a secondary row may be activated in its place may be performed. Volatile and non-volatile storage elements may be used to store the defective memory addresses. Logic circuitry in the device may match a requested address with the stored addresses and generate logic signals that trigger activation of a repaired row in place of the defective row or column. Moreover, defective rows or columns that have been previously repaired once may be further repaired. To that end, logic circuitry implementing a trumping mechanism may be used to prevent activation of multiple data rows or columns for addresses that were repaired multiple times.
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公开(公告)号：US11984185B2
公开(公告)日：2024-05-14
申请号：US17224897
申请日：2021-04-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Alan J. Wilson
CPC classification number: G11C29/76 , G11C29/025 , G11C29/789
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.
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公开(公告)号：US20240086319A1
公开(公告)日：2024-03-14
申请号：US17941592
申请日：2022-09-09
Applicant: Micron Technology, Inc.
Inventor： Donald M. Morgan , Alan J. Wilson , Bryan David Kerstetter
CPC classification number: G06F12/0292 , G11C29/10 , G06F2212/1032 , G06F2212/657
Abstract: A memory device for extending addressable array space by incorporating virtual and physical memory arrays is disclosed. When extra storage space beyond a physical memory array is needed by a controller of the memory device, the storage space may be provided by extending the address space using a virtual array. The memory device incorporates the use of an extra row address bit to increase the addressable space, whereby the extra bit is utilized to address virtual rows in the virtual array. Spare or redundant physical memory elements utilized for memory repair may be programmed to a virtual address space for the virtual memory array. When a memory device operation is activated, the extra row address bit is set to high, and the virtual row address matches with a spare or redundant memory element, the virtual row in the virtual array space is activated for performance of the operation.
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Patent Agency Ranking
公开(公告)号：US20240038284A1
公开(公告)日：2024-02-01
申请号：US17877592
申请日：2022-07-29
Applicant: Micron Technology, Inc.
Inventor： Bryan David Kerstetter , Alan J. Wilson , Donald Martin Morgan
CPC classification number: G11C7/24 , G11C7/1063 , G11C7/1066
Abstract: Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.
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公开(公告)号：US20230125544A1
公开(公告)日：2023-04-27
申请号：US17983213
申请日：2022-11-08
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , Donald M. Morgan
Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.
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公开(公告)号：US20220091978A1
公开(公告)日：2022-03-24
申请号：US17488190
申请日：2021-09-28
Applicant: Micron Technology, Inc.
Inventor： Christopher D. Wieduwilt , Alan J. Wilson
Abstract: Methods, systems, and devices for modifying subsets of memory bank operating parameters are described. First global trimming information may be configured to adjust a first subset of operating parameters for a set of memory banks within a memory system. Second global trimming information may be configured to adjust a second subset of operating parameters for the set of memory banks. Local trimming information may be used to adjust one of the subsets of the operating parameters for a subset of the memory banks. To adjust one of the subsets of the operating parameters, the local trimming information may be combined with one of the first or second global trimming information to yield additional local trimming information that is used to adjust a corresponding subset of the operating parameters at the subset of the memory banks.
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公开(公告)号：US20200265912A1
公开(公告)日：2020-08-20
申请号：US16805049
申请日：2020-02-28
Applicant: Micron Technology, Inc.
Inventor： Christopher G. Wieduwilt , Alan J. Wilson
Abstract: Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.
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公开(公告)号：US20190333601A1
公开(公告)日：2019-10-31
申请号：US16505271
申请日：2019-07-08
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , John E. Riley
Abstract: Systems and methods to perform post-packaging repair of previously repaired data groups are disclosed. The devices may have an array of addressable rows or columns of memory cells, which can be activated. Upon identification of defect in a memory cell row or column, a repair in which the memory cell may be deactivated and a secondary row may be activated in its place may be performed. Volatile and non-volatile storage elements may be used to store the defective memory addresses. Logic circuitry in the device may match a requested address with the stored addresses and generate logic signals that trigger activation of a repaired row in place of the defective row or column. Moreover, defective rows or columns that have been previously repaired once may be further repaired. To that end, logic circuitry implementing a trumping mechanism may be used to prevent activation of multiple data rows or columns for addresses that were repaired multiple times.
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