公开(公告)号：US20180025759A1

公开(公告)日：2018-01-25

申请号：US15216440

申请日：2016-07-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/08

CPC classification number: G11C7/1006 ,  G11C7/1036 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2211/4013

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.

公开(公告)号：US09805772B1

公开(公告)日：2017-10-31

申请号：US15298798

申请日：2016-10-20

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata

IPC: G11C7/06 ,  H03K19/20

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/005 ,  H03K19/20

Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.

公开(公告)号：US20240063788A1

公开(公告)日：2024-02-22

申请号：US18310805

申请日：2023-05-02

Applicant: Micron Technology, Inc.

Inventor： Raghukiran Sreeramaneni ,  Daniel B. Penney

IPC: H03K17/687 ,  G11C11/4093 ,  H03K5/1252 ,  H03K5/01

CPC classification number: H03K17/6871 ,  G11C11/4093 ,  H03K5/1252 ,  H03K5/01

Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

公开(公告)号：US11683033B2

公开(公告)日：2023-06-20

申请号：US17687959

申请日：2022-03-07

Applicant: Micron Technology, Inc.

Inventor： Raghukiran Sreeramaneni ,  Daniel B. Penney

IPC: H03K5/00 ,  H03K17/687 ,  G11C11/4093 ,  H03K5/1252 ,  H03K5/01

CPC classification number: H03K17/6871 ,  G11C11/4093 ,  H03K5/01 ,  H03K5/1252

Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

公开(公告)号：US11482265B2

公开(公告)日：2022-10-25

申请号：US17486481

申请日：2021-09-27

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4093

Abstract: A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.

公开(公告)号：US20220083239A1

公开(公告)日：2022-03-17

申请号：US17531573

申请日：2021-11-19

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/06

Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.

公开(公告)号：US20220013156A1

公开(公告)日：2022-01-13

申请号：US17486481

申请日：2021-09-27

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4093

Abstract: A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.

公开(公告)号：US11222689B2

公开(公告)日：2022-01-11

申请号：US17136760

申请日：2020-12-29

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/22

Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.

公开(公告)号：US20210173557A1

公开(公告)日：2021-06-10

申请号：US17178889

申请日：2021-02-18

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe ,  Daniel B. Penney

IPC: G06F3/06 ,  G11C8/00 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

公开(公告)号：US10854247B2

公开(公告)日：2020-12-01

申请号：US16537775

申请日：2019-08-12

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata

IPC: G11C7/06 ,  H03K19/20 ,  G11C7/08 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.