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公开(公告)号：US20150221355A1
公开(公告)日：2015-08-06
申请号：US14174405
申请日：2014-02-06
Applicant: MICRON TECHNOLOGY, INC.
CPC classification number: G11C8/18 , G11C7/109 , G11C7/1093 , G11C7/222
Abstract: An example delay circuit may include a delay block configured to receive a command signal and/or a bank address signal, a first clock signal, and a second clock signal and further configured to add an intrinsic delay to the command signal or the bank address signal and add a forward path delay greater than the intrinsic delay to the first and second clock signals.
Abstract translation: 示例延迟电路可以包括被配置为接收命令信号和/或库地址信号，第一时钟信号和第二时钟信号的延迟块，并且还被配置为向命令信号或存储体地址信号添加固有延迟 并且向第一和第二时钟信号添加大于本征延迟的前向路径延迟。
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公开(公告)号：US20250078903A1
公开(公告)日：2025-03-06
申请号：US18790372
申请日：2024-07-31
Applicant: Micron Technology, Inc.
Inventor： Huy T. Vo , Eric Carman , Kamal M. Karda
IPC: G11C11/4074 , G11C11/4091 , H10B12/00
Abstract: Systems, methods, and apparatus are provided for discharging an access device in a memory device. An example structure includes a memory device having a local sense line and a bleeder device coupled to the local sense line and a bleeder supply. The memory device can also include a sense line multiplexor coupled to the local sense line and a global sense line, and a sense amplifier coupled to the global sense line. The sense amplifier can be configured to sense and latch a voltage of the global sense line in response to the memory device receiving a command. The memory device can further include a plurality of access devices coupled to the local sense line, a plurality of capacitors coupled to the plurality of access devices, and a plate voltage supply, separate from the bleeder supply, coupled to the plurality of capacitors.
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公开(公告)号：US11715508B2
公开(公告)日：2023-08-01
申请号：US17387301
申请日：2021-07-28
Applicant: Micron Technology, Inc.
Inventor： Hyun Yoo Lee , Suryanarayana B. Tatapudi , Huy T. Vo , Ferdinando Bedeschi , Umberto Di Vincenzo , Riccardo Muzzetto
IPC: G11C11/22 , G11C11/4094 , G11C11/4091
CPC classification number: G11C11/2273 , G11C11/221 , G11C11/4091 , G11C11/4094
Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.
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公开(公告)号：US11514969B2
公开(公告)日：2022-11-29
申请号：US17381996
申请日：2021-07-21
Applicant: Micron Technology, Inc.
Inventor： Huy T. Vo , Ferdinando Bedeschi , Suryanarayana B. Tatapudi , Hyunyoo Lee , Adam S. El-Mansouri
IPC: G11C11/22
Abstract: Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.
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公开(公告)号：US20220020415A1
公开(公告)日：2022-01-20
申请号：US17381996
申请日：2021-07-21
Applicant: Micron Technology, Inc.
Inventor： Huy T. Vo , Ferdinando Bedeschi , Suryanarayana B. Tatapudi , Hyunyoo Lee , Adam S. El-Mansouri
IPC: G11C11/22
Abstract: Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.
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Patent Agency Ranking
公开(公告)号：US20210383856A1
公开(公告)日：2021-12-09
申请号：US17409608
申请日：2021-08-23
Applicant: Micron Technology, Inc.
Inventor： Huy T. Vo , Adam S. El-Mansouri , Suryanarayana B. Tatapudi , John D. Porter
IPC: G11C11/22
Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.
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公开(公告)号：US11134788B2
公开(公告)日：2021-10-05
申请号：US17165533
申请日：2021-02-02
Applicant: Micron Technology, Inc.
Inventor： Huy T. Vo , Adam S. El-Mansouri
Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.
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公开(公告)号：US11081158B2
公开(公告)日：2021-08-03
申请号：US16813334
申请日：2020-03-09
Applicant: Micron Technology, Inc.
Inventor： Hyun Yoo Lee , Suryanarayana B. Tatapudi , Huy T. Vo , Ferdinando Bedeschi , Umberto Di Vincenzo , Riccardo Muzzetto
IPC: G11C11/22 , G11C11/4094 , G11C11/4091
Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.
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公开(公告)号：US10932582B2
公开(公告)日：2021-03-02
申请号：US16867420
申请日：2020-05-05
Applicant: Micron Technology, Inc.
Inventor： Huy T. Vo , Adam S. El-Mansouri
Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.
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公开(公告)号：US10127971B1
公开(公告)日：2018-11-13
申请号：US15583023
申请日：2017-05-01
Applicant: Micron Technology, Inc.
Inventor： Scott J. Derner , Huy T. Vo , Patrick Mullarkey , Jeffrey P. Wright , Michael A. Shore
IPC: G11C11/4091 , G11C11/406 , G11C11/4072 , G11C11/4094 , G11C11/4096
Abstract: Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.
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