公开(公告)号：US20230137736A1

公开(公告)日：2023-05-04

申请号：US18048364

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Jonathan S. Parry

IPC: G06F12/1009

Abstract: Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.

公开(公告)号：US11605434B1

公开(公告)日：2023-03-14

申请号：US17462305

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Jeffrey S. McNeil ,  Giuseppe Cariello ,  Kishore Kumar Muchherla ,  Reshmi Basu

IPC: G11C11/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04

Abstract: Methods, systems, and devices for overwriting at a memory system are described. A memory system may be configured to overwrite portions of a memory array with new data, which may be associated with omitting an erase operation. For example, write operations may be performed in accordance with a first demarcation configuration to store information at a portion of a memory array. A portion of a memory system may then determine to overwrite the portion of the memory array with different or updated information, which may include performing write operations in accordance with a second demarcation configuration. The second demarcation configuration may be associated with different cell characteristics for a one or more logic states, such as different distributions of stored charge or other cell property, different demarcation characteristics, different write operations, among other differences, which may support performing an overwrite operation without first performing an erase operation.

公开(公告)号：US20230068580A1

公开(公告)日：2023-03-02

申请号：US17672026

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Chang H. Siau ,  Jonathan S. Parry

IPC: G06F3/06

Abstract: A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane.

公开(公告)号：US20220300061A1

公开(公告)日：2022-09-22

申请号：US17648394

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Jonathan S. Parry

IPC: G06F1/3234 ,  G06F1/3287

Abstract: Methods, systems, and devices for shallow hibernate power state are described. A memory system may include a memory array and a controller. The memory system may transition from a first power state having a first current to a second power state having a second current less than the first current, where the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components of the memory array. The memory system may initiate a timer after transitioning from the first power state to the second power state. The memory system may determine the timer satisfies a threshold and transition from the second power state to a third power state having a third current less than the second current based on the timer satisfying the threshold.

公开(公告)号：US20220206981A1

公开(公告)日：2022-06-30

申请号：US17573214

申请日：2022-01-11

Applicant: Micron Technology, Inc.

Inventor： Stephen D. Hanna ,  Jonathan S. Parry

IPC: G06F13/40 ,  G06F1/26

Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.

公开(公告)号：US20220188025A1

公开(公告)日：2022-06-16

申请号：US17119290

申请日：2020-12-11

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Jonathan S. Parry

IPC: G06F3/06

Abstract: Methods, systems, and devices for status information retrieval for a memory device are described. In some examples, a memory device may include a set of status registers, each of which may be configured to store a corresponding set of status information. For example, at least some of the status registers may store status information for a corresponding portion of the memory device. The memory device may receive a command to output status information along with an indication of one or more particular status registers from which to output status information in response to the command. In response to the command and indication, the memory device may output status information from any quantity of status registers, including any type of status information, in a single stream or burst.

公开(公告)号：US20220137694A1

公开(公告)日：2022-05-05

申请号：US17578273

申请日：2022-01-18

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Stephen L. Miller ,  Liang Yu

IPC: G06F1/3225 ,  G06F1/3212 ,  G06F1/3234 ,  G11C5/14 ,  H01L23/00 ,  G11C11/4074 ,  G06F1/26

Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides for converting each respective signal to a respective analog voltage to drive a common node; and utilizing a charge storage device coupled to the common node to accumulate the respective analog voltages from the dice, where the accumulated voltage indicates total power consumption of the dice.

公开(公告)号：US20220129336A1

公开(公告)日：2022-04-28

申请号：US17518170

申请日：2021-11-03

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Jonathan S. Parry ,  Giuseppe Cariello ,  Deping He

IPC: G06F11/07 ,  G06F11/30

Abstract: Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.

公开(公告)号：US20210295880A1

公开(公告)日：2021-09-23

申请号：US17339846

申请日：2021-06-04

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  George B. Raad ,  James S. Rehmeyer ,  Jonathan S. Parry

IPC: G11C5/14 ,  G11C11/00

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

公开(公告)号：US10884480B1

公开(公告)日：2021-01-05

申请号：US16548699

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Stephen L. Miller ,  Liang Yu

IPC: G11C5/14 ,  G06F1/3234 ,  G06F1/3225

Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective analog current from each respective die that corresponds to the power consumption of each respective die. The technique further provides for driving each respective analog current onto a common node that results in a cumulative analog current; and utilizing the cumulative analog current at the common node to indicate total power consumption of the dice.