公开(公告)号：US11532630B2

公开(公告)日：2022-12-20

申请号：US17004917

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu

IPC: H01L27/108 ,  G11C8/14

Abstract: Systems, methods and apparatus are provided for depositing alternating layers of dielectric material and sacrificial material in repeating iterations to form a vertical stack, forming a plurality of vertical openings through the vertical stack to form elongated vertical, pillar columns with sidewalls in the vertical stack, patterning the pillar columns to expose a location to form a channel region, selectively removing a portion of the sacrificial material to form first horizontal openings in the first horizontal direction in the sidewalls of the elongated vertical, pillar columns, and depositing a channel material in the first horizontal openings to form the channel region within the sidewalls for the horizontally oriented access devices.

公开(公告)号：US11515417B2

公开(公告)日：2022-11-29

申请号：US16596448

申请日：2019-10-08

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Ramanathan Gandhi ,  Durai Vishak Nirmal Ramaswamy ,  Yi Fang Lee ,  Kamal M. Karda

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L27/24

Abstract: A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate electrode laterally neighboring the heterogeneous channel. A device, a method of forming a device, a memory device, and an electronic system are also described.

公开(公告)号：US11488981B2

公开(公告)日：2022-11-01

申请号：US16934607

申请日：2020-07-21

Applicant: Micron Technology, Inc.

Inventor： Yi Fang Lee ,  Jaydip Guha ,  Lars P. Heineck ,  Kamal M. Karda ,  Si-Woo Lee ,  Terrence B. McDaniel ,  Scott E. Sills ,  Kevin J. Torek ,  Sheng-Wei Yang

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/13

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

公开(公告)号：US20220344468A1

公开(公告)日：2022-10-27

申请号：US17860325

申请日：2022-07-08

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Vassil N. Antonov ,  Kamal M. Karda ,  Michael Mutch ,  Hung-Wei Liu ,  Jeffery B. Hull

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.

公开(公告)号：US11476252B2

公开(公告)日：2022-10-18

申请号：US17003019

申请日：2020-08-26

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

IPC: H01L27/108 ,  G11C11/401

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.

公开(公告)号：US11469250B2

公开(公告)日：2022-10-11

申请号：US16941152

申请日：2020-07-28

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu

IPC: H01L27/1159 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/10

Abstract: Some embodiments include an integrated assembly having a ferroelectric transistor body region between a first comparative digit line and a second comparative digit line. A carrier-reservoir structure is coupled with the ferroelectric transistor body region through an extension that passes along a side of the first comparative digit line. Some embodiments include an integrated assembly having a conductive structure over a carrier-reservoir structure. A bottom of the conductive structure is spaced from the carrier-reservoir structure by an insulative region. A ferroelectric transistor is over the conductive structure. The ferroelectric transistor has a bottom source/drain region over the conductive structure, has a body region over the bottom source/drain region, and has a top source/drain region over the body region. An extension extends upwardly from the carrier-reservoir structure, along a side of the conductive structure, and to a bottom of the body region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220301941A1

公开(公告)日：2022-09-22

申请号：US17824744

申请日：2022-05-25

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Kamal M. Karda

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L27/1159 ,  H01L27/11507 ,  H01L23/528 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/792 ,  H01L27/24 ,  H01L21/8239 ,  H01L27/108

Abstract: An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.

公开(公告)号：US20220278105A1

公开(公告)日：2022-09-01

申请号：US17188083

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Litao Yang

IPC: H01L27/108 ,  H01L27/11507

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells. The vertically stacked memory cells have horizontally oriented access devices having a first source/drain region, a channel region, and a second source drain and storage nodes that are vertically separated from the access devices.

公开(公告)号：US11296094B2

公开(公告)日：2022-04-05

申请号：US16725439

申请日：2019-12-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

IPC: H01L27/108

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

公开(公告)号：US20220077320A1

公开(公告)日：2022-03-10

申请号：US17017426

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Litao Yang ,  Haitao Liu ,  Kamal M. Karda

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/49 ,  H01L27/108 ,  H01L27/11514

Abstract: Some embodiments include integrated memory. The integrated memory includes a first series of first conductive structures and a second series of conductive structures. The first conductive structures extend along a first direction. The second conductive structures extend along a second direction which crosses the first direction. Pillars of semiconductor material extend upwardly from the first conductive structures. Each of the pillars includes a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions. The lower source/drain regions are coupled with the first conductive structures. Insulative material is adjacent sidewall surfaces of the pillars. The insulative material includes ZrOx, where x is a number greater than 0. The second conductive structures include gating regions which are spaced from the channel regions by at least the insulative material. Storage elements are coupled with the upper source/drain regions.