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    SEMICONDUCTOR DEVICES INCLUDING BULB-SHAPED TRENCHES
    2.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING BULB-SHAPED TRENCHES 审中-公开
    半导体器件，包括BULB-形状的TRENCHES

    公开(公告)号：US20150340320A1

    公开(公告)日：2015-11-26

    申请号：US14817451

    申请日：2015-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Sanjeev Sapra ,  Cheng-Shun Chen ,  Hung-Ming Tsai ,  Sheng-Wei Yang

    IPC: H01L23/528 ,  H01L29/04 ,  H01L29/16

    CPC classification number: H01L23/5283 ,  B82Y30/00 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31111 ,  H01L29/04 ,  H01L29/16 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed.

    Abstract translation: 公开了一种在硅中产生一个具有一个灯泡形横截面的沟槽的方法。 该方法包括在硅中形成至少一个沟槽并在至少一个沟槽中形成衬垫。 将衬垫从至少一个沟槽的底表面移除以暴露下面的硅。 去除底层暴露的硅的一部分以在硅中形成空腔。 进行至少一个去除周期以去除空腔中的暴露的硅以形成球形横截面轮廓，每个去除周期包括使空腔中的硅经受臭氧化水以氧化硅并将氧化的硅经受 氟化氢溶液去除氧化硅。 还公开了一种半导体器件结构，其包括包括具有灯泡形横截面轮廓的空腔的至少一个沟槽。

    Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors
    3.
    发明申请
    Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors 有权

    公开(公告)号：US20230014320A1

    公开(公告)日：2023-01-19

    申请号：US17947401

    申请日：2022-09-19

    Applicant: Micron Technology, Inc.

    Inventor： Yi Fang Lee ,  Jaydip Guha ,  Lars P. Heineck ,  Kamal M. Karda ,  Si-Woo Lee ,  Terrence B. McDaniel ,  Scott E. Sills ,  Kevin J. Torek ,  Sheng-Wei Yang

    IPC: H01L27/12 ,  H01L21/84

    Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

    Array of vertical transistors and method used in forming an array of vertical transistors
    4.
    发明授权
    Array of vertical transistors and method used in forming an array of vertical transistors 有权

    公开(公告)号：US11488981B2

    公开(公告)日：2022-11-01

    申请号：US16934607

    申请日：2020-07-21

    Applicant: Micron Technology, Inc.

    Inventor： Yi Fang Lee ,  Jaydip Guha ,  Lars P. Heineck ,  Kamal M. Karda ,  Si-Woo Lee ,  Terrence B. McDaniel ,  Scott E. Sills ,  Kevin J. Torek ,  Sheng-Wei Yang

    IPC: H01L27/12 ,  H01L21/84 ,  H01L27/13

    Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

    Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors
    5.
    发明申请
    Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors 有权

    公开(公告)号：US20220028903A1

    公开(公告)日：2022-01-27

    申请号：US16934607

    申请日：2020-07-21

    Applicant: Micron Technology, Inc.

    Inventor： Yi Fang Lee ,  Jaydip Guha ,  Lars P. Heineck ,  Kamal M. Karda ,  Si-Woo Lee ,  Terrence B. McDaniel ,  Scott E. Sills ,  Kevin J. Torek ,  Sheng-Wei Yang

    IPC: H01L27/12 ,  H01L21/84

    Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

    Microelectronic devices including two contacts
    6.
    发明授权
    Microelectronic devices including two contacts 有权

    公开(公告)号：US10854514B2

    公开(公告)日：2020-12-01

    申请号：US16391600

    申请日：2019-04-23

    Applicant: Micron Technology, Inc.

    Inventor： Tieh-Chiang Wu ,  Wen-Chieh Wang ,  Sheng-Wei Yang

    IPC: H01L21/768 ,  H01L21/764 ,  H01L29/06 ,  H01L27/108 ,  H01L27/11582 ,  H01L49/02 ,  H01L29/49

    Abstract: A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps including forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer interposed in the contact layer and configured to divide the contact layer into two contacts. The method also comprises removing the dielectric layer to form a space and forming a cap layer over the two contacts to form an air gap therein. The method further comprises forming a second air gap between the conductive line and the two contacts.

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