公开(公告)号：US20240203468A1

公开(公告)日：2024-06-20

申请号：US18593635

申请日：2024-03-01

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Richard K. Dodge ,  Innocenzo Tortorelli ,  Mattia Robustelli ,  Mario Allegra

IPC: G11C7/10

CPC classification number: G11C7/1096 ,  G11C7/1051

Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).

公开(公告)号：US20230058092A1

公开(公告)日：2023-02-23

申请号：US17977046

申请日：2022-10-31

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G06F3/06 ,  G11C13/00 ,  G11C11/54 ,  G06N3/08

Abstract: An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.

公开(公告)号：US11487464B2

公开(公告)日：2022-11-01

申请号：US16503015

申请日：2019-07-03

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G06F3/06 ,  G11C13/00 ,  G11C11/54 ,  G06N3/08 ,  H01L45/00

Abstract: An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.

公开(公告)号：US11380391B2

公开(公告)日：2022-07-05

申请号：US17104547

申请日：2020-11-25

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G11C11/54 ,  G11C13/00 ,  G06N3/08 ,  G06N3/063 ,  H01L45/00

Abstract: In an example, an apparatus can include an array of memory cells and a neural memory unit controller coupled to the array of memory cells and configured to assert respective voltage pulses during a first training interval to memory cells of the array to change respective threshold voltages of the memory cells from voltages associated with a reset state to effectuate respective synaptic weight changes. The neural memory unit controller can be configured to initiate a sleep interval, during which no pulses are applied to the memory cells, to effectuate respective voltage drifts in the changed respective threshold voltages of the memory cells from a voltage associated with a set state toward the voltage associated with the reset state, and determine an output of the memory cells responsive to the respective voltage drifts in the changed respective threshold voltages after the sleep interval.

公开(公告)号：US20220108732A1

公开(公告)日：2022-04-07

申请号：US17502481

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Richard K. Dodge ,  Innocenzo Tortorelli ,  Mattia Robustelli ,  Mario Allegra

IPC: G11C7/10

Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).

公开(公告)号：US11264568B2

公开(公告)日：2022-03-01

申请号：US15223136

申请日：2016-07-29

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Mattia Boniardi ,  Enrico Varesi ,  Raffaella Calarco ,  Jos E. Boschker

IPC: H01L45/00 ,  H01L27/24

Abstract: The present disclosure includes textured memory cell structures and method of forming the same. In one or more embodiments, a memory cell includes a buffer portion formed on an amorphous portion and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation.

公开(公告)号：US20210407587A1

公开(公告)日：2021-12-30

申请号：US17370508

申请日：2021-07-08

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G11C11/54 ,  G11C13/00 ,  G11C11/56 ,  H01L45/00

Abstract: Methods, systems, and devices for mimicking neuro-biological architectures that may be present in a nervous system are described herein. A memory device may include a memory unit configured to store a value. A memory unit may include a first memory cell (e.g., an aggressor memory cell) and a plurality of other memory cells (e.g., victim memory cells). The memory unit may use thermal disturbances of the victim memory cells that may be based on an access operation to store the analog value. Thermal energy output by the aggressor memory cell during an access operation (e.g., a write operation) may cause the state of the victim memory cells to alter based on thermal relationship between the aggressor memory cell and at least some of the victim memory cells. The memory unit may be read by detecting and combining the weights of the victim memory cells during a read operation.

公开(公告)号：US20200152262A1

公开(公告)日：2020-05-14

申请号：US16733152

申请日：2020-01-02

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G11C11/54 ,  G11C13/00 ,  G11C11/56 ,  H01L45/00

Abstract: Methods, systems, and devices for mimicking neuro-biological architectures that may be present in a nervous system are described herein. A memory device may include a memory unit configured to store a value. A memory unit may include a first memory cell (e.g., an aggressor memory cell) and a plurality of other memory cells (e.g., victim memory cells). The memory unit may use thermal disturbances of the victim memory cells that may be based on an access operation to store the analog value. Thermal energy output by the aggressor memory cell during an access operation (e.g., a write operation) may cause the state of the victim memory cells to alter based on thermal relationship between the aggressor memory cell and at least some of the victim memory cells. The memory unit may be read by detecting and combining the weights of the victim memory cells during a read operation.

公开(公告)号：US20200051626A1

公开(公告)日：2020-02-13

申请号：US16102493

申请日：2018-08-13

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Agostino Pirovano ,  Innocenzo Tortorelli

IPC: G11C13/00

Abstract: Methods, systems, and devices for operating memory cell(s) are described. A resistance of a storage element included in a memory cell may be programmed by applying a voltage to the memory cell that causes ion movement within the storage element, where the storage element remains in a single phase and has different resistivity based on a location of the ions within the storage element. In some cases, multiple of such storage elements may be included in a memory cell, where ions within the storage elements respond differently to electric pulses, and a non-binary logic value may be stored in the memory cell by applying a series of voltages or currents to the memory cell.

公开(公告)号：US20190252608A1

公开(公告)日：2019-08-15

申请号：US16390939

申请日：2019-04-22

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Andrea Redaelli

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1293 ,  H01L27/2427 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

Abstract: A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.