公开(公告)号：US11966752B2

公开(公告)日：2024-04-23

申请号：US17645685

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Francesco Basso ,  Giuseppe Ferrari ,  Francesco Falanga ,  Massimo Iaculo

IPC: G06F9/44 ,  G06F9/4401 ,  G06F12/0871

CPC classification number: G06F9/4406 ,  G06F12/0871

Abstract: Methods, systems, and devices for data caching for fast system boot-up are described. A memory system may create a linked mapping of addresses, which may also be referred to as a mixed page pointer table. The linked mapping may include logical addresses associated with commands received during a boot-up procedure, and their associated physical addresses. The linked mapping may also include a counter associated with each logical address to track how often the logical address is referenced during successive boot-up procedures. Over successive boot-up procedures, addresses may be added or removed from the linked mapping, and sequential addresses may be compressed. The memory device may use the linked mapping to predict which data may be accessed during the boot-up procedure, and may pre-transfer the data to volatile memory based on the prediction.

公开(公告)号：US11720489B2

公开(公告)日：2023-08-08

申请号：US17902384

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Giuseppe Ferrari ,  Eric Kwok Fung Yuen ,  Massimo Iaculo

IPC: G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/0253 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US11675709B2

公开(公告)日：2023-06-13

申请号：US17494740

申请日：2021-10-05

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Carminantonio Manganelli ,  Paolo Papa ,  Yoav Weinberg ,  Giuseppe Ferrari ,  Massimo Iaculo ,  Lalla Fatima Drissi

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/657

Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.

公开(公告)号：US20230129539A1

公开(公告)日：2023-04-27

申请号：US17664320

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Lance W. Dover ,  Giuseppe Vito Portacci ,  Giuseppe Ferrari

IPC: G06F3/06

Abstract: Methods, systems, and devices for authenticated modification of memory system data are described. A host system may transmit a command to program data to a protection region of a memory system, and the host system may sign the command using a key associated with the protection region. In some examples, the host system may transmit the data associated with the command, or the command may include instructions to move the data from another region of the memory system. Upon receiving the command, the memory system may verify the signature to determine whether the host is authorized to modify the protection region, and may program the data as requested by the host system. In some cases, the protection regions of the memory system may be updated, for example by adjusting the size or address range of the protection regions, in response to a command from the host system.

公开(公告)号：US20220188018A1

公开(公告)日：2022-06-16

申请号：US17688304

申请日：2022-03-07

Applicant: Micron Technology, Inc.

Inventor： Eric Kwok Fung Yuen ,  Giuseppe Ferrari ,  Massimo Iaculo ,  Lalla Fatima Drissi ,  Xinghui Duan ,  Giuseppe D'Eliseo

IPC: G06F3/06 ,  G06F12/02

Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.

公开(公告)号：US20210182207A1

公开(公告)日：2021-06-17

申请号：US16713552

申请日：2019-12-13

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D`Eliseo ,  Carminantonio Manganelli ,  Paolo Papa ,  Yoav Weinberg ,  Giuseppe Ferrari ,  Massimo Laculo ,  Lalla Fatima Drissi

IPC: G06F12/1009

Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.

公开(公告)号：US20210141557A1

公开(公告)日：2021-05-13

申请号：US16075464

申请日：2017-12-21

Applicant: MICRON TECHNOLOGY INC.

Inventor： Eric Kwok Fung Yuen ,  Giuseppe Ferrari ,  Massimo Iaculo ,  Lalla Fatima Drissi ,  Xinghui Duan ,  Giuseppe D'Eliseo

IPC: G06F3/06

Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.

公开(公告)号：US10725904B2

公开(公告)日：2020-07-28

申请号：US16075543

申请日：2017-12-13

Applicant: Micron Technology, Inc.

Inventor： Zhao Cui ,  Eric Kwok Fung Yuen ,  Guan Zhong Wang ,  Xinghui Duan ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari

IPC: G06F12/02 ,  G06F12/0873

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

公开(公告)号：US20150127892A1

公开(公告)日：2015-05-07

申请号：US14536333

申请日：2014-11-07

Applicant: Micron Technology, Inc.

Inventor： Procolo Carannante ,  Angelo Di Sena ,  Fabio Salvati ,  Giuseppe Ferrari ,  Anna Sorgente

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7207 ,  G06F2212/7211 ,  Y02D10/13

Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.

Abstract translation: 一种方法包括通过将数据从第一存储器阵列的第一部分复制到第一存储器阵列的第二部分来应对磨损级操作请求，以及将与数据相关联的数据从第二存储器阵列的第三部分复制到 第二存储器阵列的第四部分。 第一存储器阵列包括NAND或基于NAND的存储器阵列，并且第二存储器阵列包括非易失性存储器，其包括由以下组成的组中的至少一个：相变存储器，EEPROM和NOR闪存。

公开(公告)号：US08924638B2

公开(公告)日：2014-12-30

申请号：US13857943

申请日：2013-04-05

Applicant: Micron Technology, Inc.

Inventor： Procolo Carannante ,  Angelo Di Sena ,  Fabio Salvati ,  Giuseppe Ferrari ,  Anna Sorgente

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7207 ,  G06F2212/7211 ,  Y02D10/13

Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.

Abstract translation: 一种方法包括通过将数据从第一存储器阵列的第一部分复制到第一存储器阵列的第二部分来应对磨损级操作请求，以及将与数据相关联的数据从第二存储器阵列的第三部分复制到 第二存储器阵列的第四部分。 第一存储器阵列包括NAND或基于NAND的存储器阵列，并且第二存储器阵列包括非易失性存储器，其包括由以下组成的组中的至少一个：相变存储器，EEPROM和NOR闪存。