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公开(公告)号：US11789661B2
公开(公告)日：2023-10-17
申请号：US17747477
申请日：2022-05-18
Applicant: Micron Technology, Inc.
Inventor： Angelo Della Monica , Eric Kwok Fung Yuen , Pasquale Cimmino , Massimo Iaculo , Francesco Falanga
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0632 , G06F3/0644 , G06F3/0679
Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US11455245B2
公开(公告)日：2022-09-27
申请号：US16076288
申请日：2017-12-11
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Giuseppe D'Eliseo , Lalla Fatima Drissi , Giuseppe Ferrari , Eric Kwok Fung Yuen , Massimo Iaculo
IPC: G06F12/02 , G06F12/1009
Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US20210182189A1
公开(公告)日：2021-06-17
申请号：US16076288
申请日：2017-12-11
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Giuseppe D'Eliseo , Lalla Fatima Drissi , Giuseppe Ferrari , Eric Kwok Fung Yuen , Massimo laculo
IPC: G06F12/02 , G06F12/1009
Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US11029883B2
公开(公告)日：2021-06-08
申请号：US16484066
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Eric Kwok Fung Yuen , Zhi Ping Yu , Guanzhong Wang
Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.
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公开(公告)号：US10754580B2
公开(公告)日：2020-08-25
申请号：US15790690
申请日：2017-10-23
Applicant: Micron Technology, Inc.
Inventor： Angelo Della Monica , Eric Kwok Fung Yuen , Pasquale Cimmino , Massimo Iaculo , Francesco Falanga
IPC: G06F3/06
Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.
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Patent Agency Ranking
公开(公告)号：US11705201B2
公开(公告)日：2023-07-18
申请号：US17409413
申请日：2021-08-23
Applicant: Micron Technology, Inc.
Inventor： Paolo Papa , Luigi Esposito , Massimo Iaculo , Eric Kwok Fung Yuen , Gerard J. Perdaems
CPC classification number: G11C16/10 , G06F3/0604 , G06F3/064 , G06F3/0619 , G06F3/0643 , G06F3/0659 , G06F3/0679 , G06F11/079 , G06F11/0727 , G06F11/0778 , G11C16/0483
Abstract: Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be written to the flash memory. The flash memory may comprise a number of storage units with each storage unit comprising a number of storage sub-units. If the first host data is less than a remainder threshold, the memory controller may generate a first program data unit comprising the first host data and first log data describing the flash memory. The memory controller may program the program data unit to the first storage unit of the flash memory, where the first log data is written to a first storage sub-unit of the number of storage sub-unit. The memory controller may also store an indication that the first storage sub-unit is invalid.
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公开(公告)号：US11604607B2
公开(公告)日：2023-03-14
申请号：US17331357
申请日：2021-05-26
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Eric Kwok Fung Yuen , Zhi Ping Yu , Guanzhong Wang
Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.
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公开(公告)号：US11340836B2
公开(公告)日：2022-05-24
申请号：US16990864
申请日：2020-08-11
Applicant: Micron Technology, Inc.
Inventor： Angelo Della Monica , Eric Kwok Fung Yuen , Pasquale Cimmino , Massimo Iaculo , Francesco Falanga
IPC: G06F3/06
Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US11269545B2
公开(公告)日：2022-03-08
申请号：US16075464
申请日：2017-12-21
Applicant: Micron Technology, Inc.
Inventor： Eric Kwok Fung Yuen , Giuseppe Ferrari , Massimo Iaculo , Lalla Fatima Drissi , Xinghui Duan , Giuseppe D'Eliseo
Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.
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公开(公告)号：US20200233606A1
公开(公告)日：2020-07-23
申请号：US16484066
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Eric Kwok Fung Yuen , Zhi Ping Yu , Guanzhong Wang
Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.
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