公开(公告)号：US20110195551A1

公开(公告)日：2011-08-11

申请号：US12962772

申请日：2010-12-08

申请人： Dae-Ik Kim

发明人： Dae-Ik Kim

IPC分类号： H01L21/8239 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L27/10885 ,  H01L21/76232 ,  H01L27/10814 ,  H01L27/10888

摘要： A semiconductor device has a bit line interconnection with a greater width and a reduced level on a bit line contact is provided, as are methods of fabricating such devices. These method includes forming a buried gate electrode to intersect an active region of a substrate. Source and drain regions are formed in the active region. A first conductive pattern is formed on the substrate. The first conductive pattern has a first conductive layer hole configured to expose the drain region. A second conductive pattern is formed in the first conductive layer hole to contact the drain region. A top surface of the second conductive pattern is at a lower level than a top surface of the first conductive pattern. A third conductive layer and a bit line capping layer are formed on the first conductive pattern and the second conductive pattern and patterned to form a third conductive pattern and a bit line capping pattern. The second conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the drain region, constitute first bit line structures, and the first conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the isolation region, constitute second bit line structures.

摘要翻译： 半导体器件具有更大宽度的位线互连，并且提供了位线触点上的降低的电平，以及制造这种器件的方法。 这些方法包括形成掩埋栅电极以与衬底的有源区相交。 源极和漏极区域形成在有源区域中。 在基板上形成第一导电图案。 第一导电图案具有被配置为暴露漏极区域的第一导电层孔。 在第一导电层孔中形成第二导电图案以接触漏区。 第二导电图案的顶表面处于比第一导电图案的顶表面更低的水平。 在第一导电图案和第二导电图案上形成第三导电层和位线封盖层，并将其图案化以形成第三导电图案和位线封盖图案。 依次堆叠在漏极区上的第二导电图案，第三导电图案和位线封盖图案构成第一位线结构，第一导电图案，第三导电图案和位线封盖图案， 其顺序地堆叠在隔离区域上，构成第二位线结构。

公开(公告)号：US07847367B2

公开(公告)日：2010-12-07

申请号：US11985511

申请日：2007-11-15

申请人： Dae-Ik Kim

发明人： Dae-Ik Kim

IPC分类号： H01L29/43 ,  H01L21/283

CPC分类号： H01L21/823437 ,  H01L27/0207

摘要： An integrated circuit device includes an integrated circuit substrate and a first gate pattern on the substrate. A non-conductive barrier layer pattern is on the first gate pattern. The barrier layer pattern has openings at selected locations therein extending to the first gate pattern. A second gate pattern is on the barrier layer pattern and extends into the opening in the barrier layer pattern to electrically connect the second gate pattern to the first gate pattern.

摘要翻译： 集成电路器件包括集成电路衬底和衬底上的第一栅极图案。 非导电阻挡层图案在第一栅极图案上。 阻挡层图案在其中延伸到第一栅极图案的选定位置处具有开口。 第二栅极图案在阻挡层图案上并延伸到阻挡层图案中的开口中，以将第二栅极图案电连接到第一栅极图案。

公开(公告)号：US08889539B2

公开(公告)日：2014-11-18

申请号：US12332877

申请日：2008-12-11

申请人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

发明人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

IPC分类号： H01L21/302 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/4236 ,  H01L29/66621

摘要： A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

摘要翻译： 提供一种形成半导体器件的方法，包括：通过图案化绝缘层在衬底上形成多个硬掩模; 在衬底中形成多个沟槽，每个沟槽具有设置在两个相邻掩模之间并且从底部到上部垂直延伸的沟槽壁; 在硬掩模和沟槽壁上形成绝缘层; 在绝缘层上形成导电层; 蚀刻导电层以形成导电层图案以填充沟槽的底部; 在导电层图案和沟槽壁上沉积缓冲层; 以及用覆盖层填充沟槽的上部。

公开(公告)号：US08507980B2

公开(公告)日：2013-08-13

申请号：US13195274

申请日：2011-08-01

申请人： Dae-Ik Kim

发明人： Dae-Ik Kim

IPC分类号： H01L29/66

CPC分类号： H01L27/10885 ,  H01L21/76232 ,  H01L27/10814 ,  H01L27/10888

摘要： A semiconductor device has a bit line interconnection with a greater width and a reduced level on a bit line contact is provided, as are methods of fabricating such devices. These method includes forming a buried gate electrode to intersect an active region of a substrate. Source and drain regions are formed in the active region. A first conductive pattern is formed on the substrate. The first conductive pattern has a first conductive layer hole configured to expose the drain region. A second conductive pattern is formed in the first conductive layer hole to contact the drain region. A top surface of the second conductive pattern is at a lower level than a top surface of the first conductive pattern. A third conductive layer and a bit line capping layer are formed on the first conductive pattern and the second conductive pattern and patterned to form a third conductive pattern and a bit line capping pattern. The second conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the drain region, constitute first bit line structures, and the first conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the isolation region, constitute second bit line structures.

摘要翻译： 半导体器件具有更大宽度的位线互连，并且提供了位线触点上的降低的电平，以及制造这种器件的方法。 这些方法包括形成掩埋栅电极以与衬底的有源区相交。 源极和漏极区域形成在有源区域中。 在基板上形成第一导电图案。 第一导电图案具有被配置为暴露漏极区域的第一导电层孔。 在第一导电层孔中形成第二导电图案以接触漏区。 第二导电图案的顶表面处于比第一导电图案的顶表面更低的水平。 在第一导电图案和第二导电图案上形成第三导电层和位线封盖层，并将其图案化以形成第三导电图案和位线封盖图案。 依次堆叠在漏极区上的第二导电图案，第三导电图案和位线封盖图案构成第一位线结构，第一导电图案，第三导电图案和位线封盖图案， 其顺序地堆叠在隔离区域上，构成第二位线结构。

公开(公告)号：US08309460B2

公开(公告)日：2012-11-13

申请号：US12662993

申请日：2010-05-14

申请人： Dae-Ik Kim ,  Ho-Jun Yi

发明人： Dae-Ik Kim ,  Ho-Jun Yi

IPC分类号： H01L21/44

CPC分类号： H01L21/76895 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

摘要： Provided are methods of manufacturing semiconductor devices by which two different kinds of contact holes with different sizes are formed using one photolithography process. The methods include preparing a semiconductor substrate in which an active region is titled in a diagonal direction. A hard mask is formed on the entire surface of the semiconductor substrate. A mask hole is patterned not to overlap a word line. A first oxide layer is deposited on the hard mask, and the hard mask is removed to form a piston-shaped sacrificial pattern. A first polysilicon (poly-Si) layer is deposited on the sacrificial pattern and patterned to form a cylindrical first sacrificial mask surrounding the piston-shaped sacrificial pattern. A second oxide layer is coated on the first sacrificial mask to such an extent as to form voids. A second poly-Si layer is deposited in the voids and patterned to form a pillar-shaped second sacrificial mask. The second oxide layer is removed to expose the active region. The sectional area of a buried contact (BC) storage contact pad may be increased, while the sectional area of a direct contact (DC) bit line contact pad may be reduced.

摘要翻译： 提供制造半导体器件的方法，通过该半导体器件，使用一个光刻工艺形成具有不同尺寸的两种不同种类的接触孔。 所述方法包括制备半导体衬底，其中活性区域在对角线方向上标称。 在半导体基板的整个表面上形成硬掩模。 图案掩模孔不与字线重叠。 在硬掩模上沉积第一氧化物层，并且去除硬掩模以形成活塞形牺牲图案。 第一多晶硅（poly-Si）层沉积在牺牲图案上并被图案化以形成围绕活塞形牺牲图案的圆柱形第一牺牲掩模。 将第二氧化物层涂覆在第一牺牲掩模上至达到形成空隙的程度。 将第二多晶硅层沉积在空隙中并图案化以形成柱状的第二牺牲掩模。 去除第二氧化物层以暴露活性区域。 埋入触点（BC）存储接触焊盘的截面积可以增加，而直接接触（DC）位线接触焊盘的截面积可能会减小。

公开(公告)号：US08198189B2

公开(公告)日：2012-06-12

申请号：US12777561

申请日：2010-05-11

申请人： Dae-Ik Kim ,  Je-Min Park ,  Chang-Suk Hyun

发明人： Dae-Ik Kim ,  Je-Min Park ,  Chang-Suk Hyun

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device includes first and second conductive structures spaced apart from one another on a substrate along a first direction. The first and second conductive structures extend in a second direction substantially perpendicular to the first direction. A contact plug is interposed between the first and second conductive structures and is separated therefrom along the first direction by respective air gaps on opposite sides of the contact plug. The air gaps define first and second air spacers that electrically insulate the contact plug from the first and second conductive structures, respectively. An upper insulation layer covers the first and second air spacers and the first and second conductive structures. The air spacers may sufficiently reduce the loading capacitance between the conductive structures. Related fabrication methods are also discussed.

摘要翻译： 集成电路器件包括沿着第一方向在衬底上彼此间隔开的第一和第二导电结构。 第一和第二导电结构在基本上垂直于第一方向的第二方向上延伸。 接触塞被插入在第一和第二导电结构之间，并且通过接触插塞的相对侧上的相应气​​隙沿第一方向与其分离。 气隙限定分别使接触塞与第一和第二导电结构电绝缘的第一和第二空气间隔件。 上绝缘层覆盖第一和第二空气间隔件以及第一和第二导电结构。 空气间隔件可以充分降低导电结构之间的负载电容。 还讨论了相关的制造方法。

公开(公告)号：US20110065275A1

公开(公告)日：2011-03-17

申请号：US12662993

申请日：2010-05-14

申请人： Dae-Ik Kim ,  Ho-Jun Yi

发明人： Dae-Ik Kim ,  Ho-Jun Yi

IPC分类号： H01L21/768

CPC分类号： H01L21/76895 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

摘要： Provided are methods of manufacturing semiconductor devices by which two different kinds of contact holes with different sizes are formed using one photolithography process. The methods include preparing a semiconductor substrate in which an active region is titled in a diagonal direction. A hard mask is formed on the entire surface of the semiconductor substrate. A mask hole is patterned not to overlap a word line. A first oxide layer is deposited on the hard mask, and the hard mask is removed to form a piston-shaped sacrificial pattern. A first polysilicon (poly-Si) layer is deposited on the sacrificial pattern and patterned to form a cylindrical first sacrificial mask surrounding the piston-shaped sacrificial pattern. A second oxide layer is coated on the first sacrificial mask to such an extent as to form voids. A second poly-Si layer is deposited in the voids and patterned to form a pillar-shaped second sacrificial mask. The second oxide layer is removed to expose the active region. The sectional area of a buried contact (BC) storage contact pad may be increased, while the sectional area of a direct contact (DC) bit line contact pad may be reduced.

摘要翻译： 提供制造半导体器件的方法，通过该半导体器件，使用一个光刻工艺形成具有不同尺寸的两种不同种类的接触孔。 所述方法包括制备半导体衬底，其中活性区域在对角线方向上标称。 在半导体基板的整个表面上形成硬掩模。 图案掩模孔不与字线重叠。 在硬掩模上沉积第一氧化物层，并且去除硬掩模以形成活塞形牺牲图案。 第一多晶硅（poly-Si）层沉积在牺牲图案上并被图案化以形成围绕活塞形牺牲图案的圆柱形第一牺牲掩模。 将第二氧化物层涂覆在第一牺牲掩模上至达到形成空隙的程度。 将第二多晶硅层沉积在空隙中并图案化以形成柱状的第二牺牲掩模。 去除第二氧化物层以暴露活性区域。 埋入触点（BC）存储接触焊盘的截面积可以增加，而直接接触（DC）位线接触焊盘的截面积可能会减小。

公开(公告)号：US20100285662A1

公开(公告)日：2010-11-11

申请号：US12777561

申请日：2010-05-11

申请人： Dae-Ik Kim ,  Je-Min Park ,  Chang-Suk Hyun

发明人： Dae-Ik Kim ,  Je-Min Park ,  Chang-Suk Hyun

IPC分类号： H01L21/768

CPC分类号： H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device includes first and second conductive structures spaced apart from one another on a substrate along a first direction. The first and second conductive structures extend in a second direction substantially perpendicular to the first direction. A contact plug is interposed between the first and second conductive structures and is separated therefrom along the first direction by respective air gaps on opposite sides of the contact plug. The air gaps define first and second air spacers that electrically insulate the contact plug from the first and second conductive structures, respectively. An upper insulation layer covers the first and second air spacers and the first and second conductive structures. The air spacers may sufficiently reduce the loading capacitance between the conductive structures. Related fabrication methods are also discussed.

摘要翻译： 集成电路器件包括沿着第一方向在衬底上彼此间隔开的第一和第二导电结构。 第一和第二导电结构在基本上垂直于第一方向的第二方向上延伸。 接触塞被插入在第一和第二导电结构之间，并且通过接触插塞的相对侧上的相应气​​隙沿第一方向与其分离。 气隙限定分别使接触塞与第一和第二导电结构电绝缘的第一和第二空气间隔件。 上绝缘层覆盖第一和第二空气间隔件以及第一和第二导电结构。 空气间隔件可以充分降低导电结构之间的负载电容。 还讨论了相关的制造方法。

公开(公告)号：US20080111208A1

公开(公告)日：2008-05-15

申请号：US11985511

申请日：2007-11-15

申请人： Dae-Ik Kim

发明人： Dae-Ik Kim

IPC分类号： H01L29/43 ,  H01L21/283

CPC分类号： H01L21/823437 ,  H01L27/0207

摘要： An integrated circuit device includes an integrated circuit substrate and a first gate pattern on the substrate. A non-conductive barrier layer pattern is on the first gate pattern. The barrier layer pattern has openings at selected locations therein extending to the first gate pattern. A second gate pattern is on the barrier layer pattern and extends into the opening in the barrier layer pattern to electrically connect the second gate pattern to the first gate pattern.

摘要翻译： 集成电路器件包括集成电路衬底和衬底上的第一栅极图案。 非导电阻挡层图案在第一栅极图案上。 阻挡层图案在其中延伸到第一栅极图案的选定位置处具有开口。 第二栅极图案在阻挡层图案上并延伸到阻挡层图案中的开口中，以将第二栅极图案电连接到第一栅极图案。

公开(公告)号：US20050218448A1

公开(公告)日：2005-10-06

申请号：US11083457

申请日：2005-03-18

申请人： Dae-Ik Kim ,  Joon-Mo Kwon ,  Byung-Hak Lee

发明人： Dae-Ik Kim ,  Joon-Mo Kwon ,  Byung-Hak Lee

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/108

CPC分类号： H01L21/823456 ,  H01L21/823425 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A transistor structure and a method of forming the same prevent a boundary face of first and second gate electrodes from being oxidized in a subsequent oxidation process, by forming an oxidation inhibition layer in the boundary face. A gate insulation layer is formed on a semiconductor substrate, and a gate stack is obtained by a sequential accumulation of first and second gate electrodes and a capping layer on the gate insulation layer. An oxidation inhibition layer is formed in a sidewall portion of the gate stack, and the oxidation inhibition layer covers a boundary face of the first and second gate electrodes. Source/drain regions are opposite to the gate stack.

摘要翻译： 晶体管结构及其形成方法通过在边界面中形成氧化抑制层，防止第一和第二栅极的边界面在随后的氧化过程中被氧化。 在半导体衬底上形成栅极绝缘层，并且通过栅极绝缘层上的第一和第二栅电极和覆盖层的顺序堆积来获得栅叠层。 在栅极堆叠的侧壁部分形成氧化抑制层，氧化抑制层覆盖第一和第二栅电极的边界面。 源极/漏极区域与栅极堆叠相反。