公开(公告)号：US20050251631A1

公开(公告)日：2005-11-10

申请号：US11182123

申请日：2005-07-15

申请人： Joseph Rowlands ,  Manu Gulati

发明人： Joseph Rowlands ,  Manu Gulati

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0824

摘要： A shared memory system includes a plurality of processing nodes and a packetized input/output link. Each of the plurality of processing nodes includes a processing resource and memory. The packetized I/O link operably couples the plurality of processing nodes together. One of the plurality of processing nodes is operably coupled to: initiate coherent memory transactions such that another one of plurality of processing nodes has access to a home memory section of the memory of the one of the plurality of processing nodes; and facilitate transmission of a coherency transaction packet between the memory of the one of the plurality of processing nodes and the another one of the plurality of processing nodes over the packetized I/O link.

摘要翻译： 共享存储器系统包括多个处理节点和分组化的输入/输出链路。 多个处理节点中的每一个包括处理资源和存储器。 打包的I / O链路将多个处理节点可操作地耦合在一起。 多个处理节点中的一个可操作地耦合到：发起相干存储器事务，使得多个处理节点中的另一个处理节点可以访问多个处理节点之一的存储器的归属存储器部分; 并且便于通过分组化的I / O链路在多个处理节点之一的存储器与多个处理节点中的另一个处理节点之间传输一致性事务分组。

公开(公告)号：US20050226234A1

公开(公告)日：2005-10-13

申请号：US11146449

申请日：2005-06-07

申请人： Barton Sano ,  Joseph Rowlands ,  James Keller ,  Laurent Moll ,  Koray Oner ,  Manu Gulati

发明人： Barton Sano ,  Joseph Rowlands ,  James Keller ,  Laurent Moll ,  Koray Oner ,  Manu Gulati

IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F13/14 ,  G06F13/28 ,  G06F13/36 ,  G06F15/167 ,  H04L12/56 ,  H04Q11/00

CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

摘要翻译： 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

公开(公告)号：US20050223188A1

公开(公告)日：2005-10-06

申请号：US11146450

申请日：2005-06-07

申请人： Laurent Moll ,  James Kelly ,  Manu Gulati ,  Koray Oner ,  Joseph Rowlands

发明人： Laurent Moll ,  James Kelly ,  Manu Gulati ,  Koray Oner ,  Joseph Rowlands

IPC分类号： G06F3/00 ,  G06F9/42 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F13/1684

摘要： A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

摘要翻译： 节点包括耦合到节点内的互连的至少一个代理和输入/输出（I / O）电路。 I / O电路被配置为在使用期间一个或多个其他节点耦合到的全局互连上进行通信。 在互连上发送的地址在节点的第一本地地址空间中，并且在全局互连上发送的地址在全局地址空间中。 第一本地地址空间至少包括用于寻址节点的至少第一资源的第一区域。 该节点在使用期间是可编程的，以重新定位第一本地地址空间内的第一区域，由此第一本地地址空间中的相同数值和对应于耦合到全局互连的其他节点之一的第二本地地址空间 到使用中的节点的第一个资源。

公开(公告)号：US06944719B2

公开(公告)日：2005-09-13

申请号：US10356321

申请日：2003-01-31

申请人： Joseph B. Rowlands ,  Manu Gulati

发明人： Joseph B. Rowlands ,  Manu Gulati

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0824

摘要： A packetized I/O link such as the HyperTransport protocol is adapted to transport memory coherency transactions over the link to support cache coherency in distributed shared memory systems. The I/O link protocol is adapted to include additional virtual channels that can carry command packets for coherency transactions over the link in a format that is acceptable to the I/O protocol. The coherency transactions support cache coherency between processing nodes interconnected by the link. Each processing node may include processing resources that themselves share memory, such as symmetrical multiprocessor configuration. In this case, coherency will have to be maintained both at the intranode level as well as the internode level. A remote line directory is maintained by each processing node so that it can track the state and location of all of the lines from its local memory that have been provided to other remote nodes. A node controller initiates transactions over the link in response to local transactions initiated within itself, and initiates transactions over the link based on local transactions initiated within itself. Flow control is provided for each of the coherency virtual channels either by software through credits or through a buffer free command packet that is sent to a source node by a target node indicating the availability of virtual channel buffering for that channel.

摘要翻译： 诸如HyperTransport协议的分组化I / O链路适于通过链路传送存储器一致性事务以支持分布式共享存储器系统中的高速缓存一致性。 I / O链路协议适于包括可以以I / O协议可接受的格式在链路上携带用于一致性事务的命令分组的附加虚拟通道。 相关事务支持通过链路互连的处理节点之间的高速缓存一致性。 每个处理节点可以包括它们共享存储器的处理资源，例如对称多处理器配置。 在这种情况下，必须在内部级别以及节点间级别保持一致性。 每个处理节点维护远程线路目录，以便它可以跟踪已经提供给其他远程节点的本地存储器中的所有线路的状态和位置。 响应于本身发起的本地事务，节点控制器通过链路发起事务，并且基于本身发起的本地事务来发起链路上的事务。 通过软件通过信用或通过由目标节点发送到源节点的无缓冲器命令分组来为每个相关虚拟信道提供流量控制，指示该信道的虚拟信道缓冲的可用性。

公开(公告)号：US09009541B2

公开(公告)日：2015-04-14

申请号：US13590159

申请日：2012-08-20

申请人： Manu Gulati ,  James D. Ramsay ,  Kevin R. Walker

发明人： Manu Gulati ,  James D. Ramsay ,  Kevin R. Walker

IPC分类号： G06F11/34 ,  G06F11/22 ,  G06F12/08

CPC分类号： G06F11/22 ,  G06F11/3013 ,  G06F11/3476 ,  G06F11/348 ,  G06F11/349 ,  G06F11/3636 ,  G06F11/366 ,  G06F12/084 ,  G06F2201/805 ,  Y02D10/13 ,  Y02D10/34

摘要： A system and method for efficiently storing traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes a trace buffer with multiple physical partitions assigned to subsets of the multiple buses. The number of partitions is less than the number of multiple buses. One or more trace instructions may cause a trace history, trace bus event statistics, local time stamps and a global time-base value to be stored in a physical partition within the trace buffer.

摘要翻译： 一种用于在嵌入式系统中高效存储多个组件的轨迹的系统和方法。 系统级芯片（SOC）包括用于收集和存储跟踪历史，总线事件统计信息或两者的跟踪单元。 SOC可以在共享存储器和高速缓存一致控制器之间的多个总线上传送高速缓存相干消息。 跟踪单元包括具有分配给多个总线的子集的多个物理分区的跟踪缓冲器。 分区的数量少于多个总线的数量。 一个或多个跟踪指令可能会导致跟踪历史记录，跟踪总线事件统计信息，本地时间戳和全局时基值存储在跟踪缓冲区中的物理分区中。

公开(公告)号：US20070291781A1

公开(公告)日：2007-12-20

申请号：US11803637

申请日：2007-05-15

申请人： Barton Sano ,  Laurent Moll ,  Manu Gulati

发明人： Barton Sano ,  Laurent Moll ,  Manu Gulati

IPC分类号： H04L12/56

CPC分类号： H04L47/40

摘要： An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.

公开(公告)号：US07979573B2

公开(公告)日：2011-07-12

申请号：US10421988

申请日：2003-04-23

申请人： Manu Gulati

发明人： Manu Gulati

IPC分类号： G06F15/173

CPC分类号： H04L49/252

摘要： Smart routing between peers in a point-to-point link based system begins when a device of a plurality of devices in a point-to-point link interconnected system receives a packet from an upstream link or a downstream link. The processing continues when the device interprets the packet to determine a destination of the packet. If the device is the destination of the packet, the device accepts the packet. If, however, the device is not the destination of the packet, the device forwards the packet on another upstream link or another downstream link without alteration of at least one of: source information of the packet and destination information of the packet.

摘要翻译： 基于点对点链路的系统中的对等体之间的智能路由开始于点对点链路互连系统中的多个设备的设备从上游链路或下游链路接收到分组。 当设备解释分组以确定分组的目的地时，处理继续。 如果设备是报文的目的地，则设备接受报文。 然而，如果设备不是分组的目的地，则设备在另一上游链路或另一下游链路上转发分组，而不改变分组的源信息和分组的目的地信息中的至少一个。

公开(公告)号：US07346078B2

公开(公告)日：2008-03-18

申请号：US10356324

申请日：2003-01-31

申请人： Manu Gulati ,  Laurent Moll ,  James Keller

发明人： Manu Gulati ,  Laurent Moll ,  James Keller

IPC分类号： H04J3/22

CPC分类号： G06F13/4247

摘要： A multiple processor device stores a stream of data as a plurality of data segments, which includes multiplexed data fragments from at least one of a plurality of virtual channels. The data segments that comprise the stream of data correspond to the multiplexed data fragments from the virtual channels. The multiple processor device then decodes at least one data segment in accordance with one of a plurality of transmission protocols to produce a decoded data segment. The multiple processor device then stores the decoded data segment to align it in accordance with a data path segment size. The multiple processor device then interprets the stored decoded data segment with respect to a corresponding one of the plurality of virtual channels to determine a destination of the stored decoded data segment. The multiple processor device then stores the decoded data segment as part of reassembled data.

摘要翻译： 多处理器设备将数据流存储为多个数据段，其包括来自多个虚拟通道中的至少一个的多路复用数据片段。 构成数据流的数据段对应于来自虚拟通道的复用数据片段。 多处理器设备然后根据多个传输协议之一对至少一个数据段进行解码，以产生解码的数据段。 然后，多处理器设备存储解码的数据段，以根据数据路径段大小进行对准。 然后，多处理器设备相对于多个虚拟通道中的相应一个解码存储的解码数据段，以确定存储的解码数据段的目的地。 然后，多处理器设备将解码的数据段存储为重新组装的数据的一部分。

公开(公告)号：US20070214230A1

公开(公告)日：2007-09-13

申请号：US11717511

申请日：2007-03-13

申请人： Barton Sano ,  Joseph Rowlands ,  Laurent Moll ,  Manu Gulati

发明人： Barton Sano ,  Joseph Rowlands ,  Laurent Moll ,  Manu Gulati

IPC分类号： G06F15/167

CPC分类号： G06F13/4022

摘要： An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

公开(公告)号：US09183147B2

公开(公告)日：2015-11-10

申请号：US13590150

申请日：2012-08-20

申请人： Manu Gulati ,  James D. Ramsay ,  Kevin R. Walker

发明人： Manu Gulati ,  James D. Ramsay ,  Kevin R. Walker

IPC分类号： G06F12/08

CPC分类号： G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  Y02D10/13

摘要： A system and method for efficiently monitoring traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes multiple bus event filters. Programmable configuration registers are used to assign the bus event filters to selected buses for monitoring associated bus traffic and determining whether qualified bus events occur. If so, the bus event filters increment an associated count for each of the qualified bus events. The values used for determining qualified bus events may be set by programmable configuration registers.

摘要翻译： 一种用于高效监控嵌入式系统中多个组件的跟踪的系统和方法。 系统级芯片（SOC）包括用于收集和存储跟踪历史，总线事件统计信息或两者的跟踪单元。 SOC可以在共享存储器和高速缓存一致控制器之间的多个总线上传送高速缓存相干消息。 跟踪单元包括多个总线事件过滤器。 可编程配置寄存器用于将总线事件滤波器分配给选定的总线，用于监视相关的总线流量并确定是否发生合格的总线事件。 如果是这样，总线事件过滤器会为每个合格的总线事件增加相关的计数。 用于确定合格总线事件的值可以由可编程配置寄存器设置。