公开(公告)号：US20050223188A1

公开(公告)日：2005-10-06

申请号：US11146450

申请日：2005-06-07

申请人： Laurent Moll ,  James Kelly ,  Manu Gulati ,  Koray Oner ,  Joseph Rowlands

发明人： Laurent Moll ,  James Kelly ,  Manu Gulati ,  Koray Oner ,  Joseph Rowlands

IPC分类号： G06F3/00 ,  G06F9/42 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F13/1684

摘要： A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

摘要翻译： 节点包括耦合到节点内的互连的至少一个代理和输入/输出（I / O）电路。 I / O电路被配置为在使用期间一个或多个其他节点耦合到的全局互连上进行通信。 在互连上发送的地址在节点的第一本地地址空间中，并且在全局互连上发送的地址在全局地址空间中。 第一本地地址空间至少包括用于寻址节点的至少第一资源的第一区域。 该节点在使用期间是可编程的，以重新定位第一本地地址空间内的第一区域，由此第一本地地址空间中的相同数值和对应于耦合到全局互连的其他节点之一的第二本地地址空间 到使用中的节点的第一个资源。

公开(公告)号：US20050226234A1

公开(公告)日：2005-10-13

申请号：US11146449

申请日：2005-06-07

申请人： Barton Sano ,  Joseph Rowlands ,  James Keller ,  Laurent Moll ,  Koray Oner ,  Manu Gulati

发明人： Barton Sano ,  Joseph Rowlands ,  James Keller ,  Laurent Moll ,  Koray Oner ,  Manu Gulati

IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F13/14 ,  G06F13/28 ,  G06F13/36 ,  G06F15/167 ,  H04L12/56 ,  H04Q11/00

CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

摘要翻译： 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

公开(公告)号：US20050147105A1

公开(公告)日：2005-07-07

申请号：US11069313

申请日：2005-03-01

申请人： Barton Sano ,  Koray Oner ,  Laurent Moll ,  Manu Gulati

发明人： Barton Sano ,  Koray Oner ,  Laurent Moll ,  Manu Gulati

IPC分类号： G06F13/28 ,  H04L12/56

CPC分类号： H04L49/10 ,  H04L49/602

摘要： An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.

公开(公告)号：US20070214230A1

公开(公告)日：2007-09-13

申请号：US11717511

申请日：2007-03-13

申请人： Barton Sano ,  Joseph Rowlands ,  Laurent Moll ,  Manu Gulati

发明人： Barton Sano ,  Joseph Rowlands ,  Laurent Moll ,  Manu Gulati

IPC分类号： G06F15/167

CPC分类号： G06F13/4022

摘要： An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

公开(公告)号：US20050080953A1

公开(公告)日：2005-04-14

申请号：US10685129

申请日：2003-10-14

申请人： Koray Oner ,  Laurent Moll

发明人： Koray Oner ,  Laurent Moll

IPC分类号： G06F3/00 ,  G06F13/16 ,  G06F13/40

CPC分类号： G06F13/4018 ,  G06F13/1678

摘要： A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a packet data transfer circuit that uses a fragment storage buffer to align and/or merge data being transferred to or from memory on a plurality of channels. In a packet reception embodiment, a data shifter and fragment store buffer are used to align received packet data to any required offset. The aligned data may and then be written to the system bus or combined with data fragments from prior data cycles before being written to the system bus. When packet data is being transferred to memory on a plurality of channels, the fragment storage may be channelized using register files or flip-flops to store intermediate values of packets and states for each channel.

摘要翻译： 在单个CMOS集成电路上基本实现的多处理器切换装置结合分组数据传输电路进行描述，分组数据传输电路使用分段存储缓冲器来对准和/或合并正在或从多个通道上的存储器传送的数据。 在分组接收实施例中，使用数据移位器和片段存储缓冲器来将接收的分组数据对准任何所需的偏移。 在写入系统总线之前，对齐的数据可以然后被写入系统总线或与来自先前数据周期的数据片段组合。 当分组数据被传送到多个信道上的存储器时，片段存储可以使用寄存器文件或触发器被信道化，以存储每个信道的分组和状态的中间值。

公开(公告)号：US07243172B2

公开(公告)日：2007-07-10

申请号：US10685129

申请日：2003-10-14

申请人： Koray Oner ,  Laurent Moll

发明人： Koray Oner ,  Laurent Moll

IPC分类号： G06F13/38

CPC分类号： G06F13/4018 ,  G06F13/1678

摘要： A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a packet data transfer circuit that uses a fragment storage buffer to align and/or merge data being transferred to or from memory on a plurality of channels. In a packet reception embodiment, a data shifter and fragment store buffer are used to align received packet data to any required offset. The aligned data may and then be written to the system bus or combined with data fragments from prior data cycles before being written to the system bus. When packet data is being transferred to memory on a plurality of channels, the fragment storage may be channelized using register files or flip-flops to store intermediate values of packets and states for each channel.

摘要翻译： 在单个CMOS集成电路上基本实现的多处理器切换装置结合分组数据传输电路进行描述，分组数据传输电路使用分段存储缓冲器来对准和/或合并正在或从多个通道上的存储器传送的数据。 在分组接收实施例中，使用数据移位器和片段存储缓冲器来将接收的分组数据对准任何所需的偏移。 在写入系统总线之前，对齐的数据可以然后被写入系统总线或与来自先前数据周期的数据片段组合。 当分组数据被传送到多个信道上的存储器时，片段存储可以使用寄存器文件或触发器被信道化，以存储每个信道的分组和状态的中间值。

公开(公告)号：US20070291781A1

公开(公告)日：2007-12-20

申请号：US11803637

申请日：2007-05-15

申请人： Barton Sano ,  Laurent Moll ,  Manu Gulati

发明人： Barton Sano ,  Laurent Moll ,  Manu Gulati

IPC分类号： H04L12/56

CPC分类号： H04L47/40

摘要： An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.

公开(公告)号：US20070189299A1

公开(公告)日：2007-08-16

申请号：US11786275

申请日：2007-04-11

申请人： Manu Gulati ,  Laurent Moll ,  James Keller

发明人： Manu Gulati ,  Laurent Moll ,  James Keller

IPC分类号： H04L12/56 ,  H04L12/54

CPC分类号： G06F13/4247

摘要： A method for receiving data from a plurality of virtual channels begins by storing a stream of data as a plurality of data segments, wherein the stream of data includes multiplexed data fragments from at least one of the plurality of virtual channels, and wherein a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The method continues by decoding at least one of the plurality of data segments in accordance with one of a plurality of data transmission protocols to produce at least one decoded data segment. The method continues by storing the at least one decoded data segment, in a generic format, to reassemble at least a portion of a packet provided by the at least one of the plurality of virtual channels. The method continues by routing the at least one decoded data segment as at least part of the reassembled packet to one of a plurality of destinations in accordance with the at least one of the plurality of virtual channels.

摘要翻译： 用于从多个虚拟频道接收数据的方法开始于将数据流存储为多个数据段，其中数据流包括来自多个虚拟通道中的至少一个的多路复用数据片段，并且其中数据段 所述多个数据段对应于所述多路复用数据片段中的一个。 该方法通过根据多个数据传输协议之一对多个数据段中的至少一个解码以产生至少一个解码的数据段来继续。 该方法通过以通用格式存储至少一个解码的数据段来重新组合由多个虚拟通道中的至少一个提供的分组的至少一部分来继续。 该方法通过根据多个虚拟信道中的至少一个将至少一个解码的数据段作为至少部分重新组装的分组路由到多个目的地之一来继续。

公开(公告)号：US08208470B2

公开(公告)日：2012-06-26

申请号：US12573754

申请日：2009-10-05

申请人： Manu Gulati ,  Laurent Moll ,  Barton Sano

发明人： Manu Gulati ,  Laurent Moll ,  Barton Sano

IPC分类号： H04L12/28

CPC分类号： H04L12/56

摘要： A multiple processor device generates a control packet for at least one connectionless-based packet in partial accordance with a control packet format of the connection-based point-to-point link and partially not in accordance with the control packet format. For instance, the multiple processor device generates the control packet to include, in noncompliance with the control packet format, one or more of an indication that at least one connectionless-based packet is being transported, an indication of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet, an indication of an amount of data included in the associated data packet, status of the at least one connectionless-based packet, and an error status indication. The multiple processor device then generates the associated data packet in accordance with a data packet format of the connection-based point-to-point link, wherein the data packet includes at least a portion of the at least one connectionless-based packet.

摘要翻译： 多处理器设备部分地根据基于连接的点对点链路的控制分组格式生成用于至少一个基于无连接的分组的控制分组，并且部分地不符合控制分组格式。 例如，多处理器设备生成控制分组，以在不遵守控制分组格式的情况下包括以下指示：至少一个基于无连接的分组正被传输的指示，多个 与至少一个基于无连接的分组关联的虚拟频道，包括在相关数据分组中的数据量的指示，至少一个基于无连接的分组的状态以及错误状态指示。 然后，多处理器设备根据基于连接的点对点链路的数据分组格式生成相关联的数据分组，其中数据分组包括至少一个基于无连接的分组的至少一部分。

公开(公告)号：US20100020816A1

公开(公告)日：2010-01-28

申请号：US12573754

申请日：2009-10-05

申请人： Manu Gulati ,  Laurent Moll ,  Barton Sano

发明人： Manu Gulati ,  Laurent Moll ,  Barton Sano

IPC分类号： H04L12/56 ,  H04L29/06

CPC分类号： H04L12/56

摘要： A multiple processor device generates a control packet for at least one connectionless-based packet in partial accordance with a control packet format of the connection-based point-to-point link and partially not in accordance with the control packet format. For instance, the multiple processor device generates the control packet to include, in noncompliance with the control packet format, one or more of an indication that at least one connectionless-based packet is being transported, an indication of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet, an indication of an amount of data included in the associated data packet, status of the at least one connectionless-based packet, and an error status indication. The multiple processor device then generates the associated data packet in accordance with a data packet format of the connection-based point-to-point link, wherein the data packet includes at least a portion of the at least one connectionless-based packet.

摘要翻译： 多处理器设备部分地根据基于连接的点对点链路的控制分组格式生成用于至少一个基于无连接的分组的控制分组，并且部分地不符合控制分组格式。 例如，多处理器设备生成控制分组，以在不遵守控制分组格式的情况下包括以下指示：至少一个基于无连接的分组正被传输的指示，多个 与至少一个基于无连接的分组关联的虚拟频道，包括在相关数据分组中的数据量的指示，至少一个基于无连接的分组的状态以及错误状态指示。 然后，多处理器设备根据基于连接的点对点链路的数据分组格式生成相关联的数据分组，其中数据分组包括至少一个基于无连接的分组的至少一部分。